利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

239 条记录 (耗时 0.124 秒)

    Multi-state thermally assisted storage
    182.
    发明申请
    Multi-state thermally assisted storage 有权
    多状态热辅助存储

    公开(公告)号：US20080160641A1

    公开(公告)日：2008-07-03

    申请号：US12012576

    申请日：2008-02-04

    申请人： Tai Min ,  Po-Kang Wang

    发明人： Tai Min ,  Po-Kang Wang

    IPC分类号： H01L21/00

    CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/5607

    摘要： A process for manufacturing a random access memory cell, that is capable of storing multiple information states in a single physical bit, is described. The basic structure combines a conventional MTJ with a reference stack that is magnetostatically coupled to the MTJ. The MTJ is read in the usual way but data is written and stored in the reference stack. Through use of two bit lines, the direction of magnetization of the free layer can be changed in small increments each unique direction representing a different information state.

    摘要翻译： 描述了能够在单个物理位中存储多个信息状态的随机存取存储器单元的制造过程。 基本结构将传统的MTJ与静磁耦合到MTJ的参考堆叠相结合。 MTJ以通常的方式读取，但是数据被写入并存储在参考堆栈中。 通过使用两个位线，自由层的磁化方向可以以小的增量改变每个独特的方向代表不同的信息状态。

    Spin transfer MRAM device with magnetic biasing
    183.
    发明申请
    Spin transfer MRAM device with magnetic biasing 有权
    具有磁偏置的自旋转移MRAM器件

    公开(公告)号：US20080151614A1

    公开(公告)日：2008-06-26

    申请号：US11644132

    申请日：2006-12-22

    申请人： Yimin Guo

    发明人： Yimin Guo

    IPC分类号： G11C11/00 ,  H01L29/82 ,  H01L21/00

    CPC分类号： G11C11/16 ,  G11C11/161 ,  G11C11/1675

    摘要： The addition of segmented write word lines to a spin-transfer MRAM structure serves to magnetically bias the free layer so that the precessional motion of the magnetization vector that is set in play by the flow of spin polarized electrons into the free layer allows said magnetic vector to be switched rather than to oscillate between two easy axis directions.

    摘要翻译： 将分段写入字线添加到自旋转移MRAM结构中用于对自由层进行磁偏置，使得通过自旋极化电子流入自由层而设置的磁化矢量的进动运动允许所述磁矢量 而不是在两个易轴方向之间振荡。

    Bottom conductor for integrated MRAM
    184.
    发明申请
    Bottom conductor for integrated MRAM 有权
    集成MRAM的底部导体

    公开(公告)号：US20070281427A1

    公开(公告)日：2007-12-06

    申请号：US11891923

    申请日：2007-08-14

    申请人： Wei Cao ,  Chyu-Jiuh Torng ,  Cheng Horng ,  Ruying Tong ,  Chen-Jung Chien ,  Liubo Hong

    发明人： Wei Cao ,  Chyu-Jiuh Torng ,  Cheng Horng ,  Ruying Tong ,  Chen-Jung Chien ,  Liubo Hong

    IPC分类号： H01L21/336

    CPC分类号： H01L43/12 ,  H01L27/228

    摘要： A method to fabricate an MTJ device and its connections to a CMOS integrated circuit is described. The device is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its smoothness, its compatibility with the inter-layer dielectric materials, and its ability to protect the underlying tantalum.

    摘要翻译： 描述了制造MTJ器件及其与CMOS集成电路的连接的方法。 该设备由三层构建。 底层用作中心层的种子层，其为α钽，而第三最顶层选择为其平滑度，其与层间电介质材料的相容性以及其保护下面的钽的能力。

    Method of forming super-paramagnetic cladding material on conductive lines of MRAM devices
    185.
    发明授权
    Method of forming super-paramagnetic cladding material on conductive lines of MRAM devices 失效
    在MRAM器件的导线上形成超顺磁覆层材料的方法

    公开(公告)号：US07304360B2

    公开(公告)日：2007-12-04

    申请号：US11179251

    申请日：2005-07-12

    申请人： Yimin Guo ,  Po-Kang Wang

    发明人： Yimin Guo ,  Po-Kang Wang

    IPC分类号： H01L29/82

    CPC分类号： G11C11/16

    摘要： A super-paramagnetic cladding layer formed on from 1 to 3 sides of a conductive line in a magnetic device is disclosed. The cladding layer is made of “x” ML/SL stacks in which x is between 5 and 50, SL is an amorphous AlOx seed layer, and ML is a composite with a soft magnetic layer comprised of discontinuous particles less than 2 nm in size on the seed layer and a capping layer of Ru, Ta, or Cu on the soft magnetic layer. Fringing fields and hysteresis effects from continuous ferromagnetic cladding layers associated with switching the magnetic state of an adjacent MTJ are totally eliminated because of the super-paramagnetic character of the soft magnetic layer at room temperature. The soft magnetic layer has near zero magnetostriction, very high susceptibility, and may be made of Ni˜80Fe˜20, Ni˜30Fe˜70, Co˜90Fe˜10, or CoNiFe.

    摘要翻译： 公开了一种形成在磁性装置中的导线的1至3侧的超顺磁覆层。 包层由“x”ML / SL堆叠制成，其中x在5和50之间，SL是无定形AlO x种子层，ML是具有由以下组成的软磁性层的复合材料： 在种子层上尺寸小于2nm的不连续粒子和软磁层上的Ru，Ta或Cu的覆盖层。 由于在室温下软磁性层的超顺磁特性，完全消除了与切换相邻MTJ的磁状态相关联的连续铁磁覆层的起始场和滞后效应。 软磁性层具有接近零的磁致伸缩性，非常高的磁化率，并且可以由Ni-80Fe-20，Ni-30Fe CoNiFe，或CoNiFe。

    Bottom conductor for integrated MRAM
    186.
    发明授权
    Bottom conductor for integrated MRAM 有权
    集成MRAM的底部导体

    公开(公告)号：US07265404B2

    公开(公告)日：2007-09-04

    申请号：US11215276

    申请日：2005-08-30

    申请人： Wei Cao ,  Chyu-Jiuh Torng ,  Cheng Horng ,  Ruying Tong ,  Chen-Jung Chien ,  Liubo Hong

    发明人： Wei Cao ,  Chyu-Jiuh Torng ,  Cheng Horng ,  Ruying Tong ,  Chen-Jung Chien ,  Liubo Hong

    IPC分类号： H01L29/76

    CPC分类号： H01L43/12 ,  H01L27/228

    摘要： A structure that is well suited to connecting an MTJ device to a CMOS integrated circuit is described. It is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its smoothness, its compatibility with the inter-layer dielectric materials, and its ability to protect the underlying tantalum. A method for its formation is also described.

    摘要翻译： 描述了非常适合于将MTJ设备连接到CMOS集成电路的结构。 它由三层构建。 底层用作中心层的种子层，其为α钽，而第三最顶层选择为其平滑度，其与层间电介质材料的相容性以及其保护下面的钽的能力。 还描述了其形成方法。

    MRAM with split read-write cell structures
    187.
    发明申请
    MRAM with split read-write cell structures 失效
    具有分割读写单元结构的MRAM

    公开(公告)号：US20070164380A1

    公开(公告)日：2007-07-19

    申请号：US11331998

    申请日：2006-01-13

    申请人： Tai Min ,  Po-Kang Wang

    发明人： Tai Min ,  Po-Kang Wang

    IPC分类号： H01L43/00

    CPC分类号： H01L27/228

    摘要： An MRAM cell is formed in two separate portions. A first portion, that includes a pinned layer, a tunneling barrier layer and first free layer part, is used to read the value of a stored bit of information. A second portion includes a second free layer part on which information is written and stored. The second free layer part is formed with a high aspect ratio cross-section that renders it strongly magnetically anisotropic and enables it to couple to the relatively isotropic first free layer through a magnetostatic interaction. This interaction aligns the magnetization of the first free layer part in an opposite direction to the magnetization of the second free layer part. The magnetic orientation of the first free layer part relative to that of its adjacent pinned layer determines the resistance state of the first cell portion and this resistance state can be read by passing a current through the first cell portion. Thus, in effect, the first cell portion becomes a remote sensing device for the magnetization orientation of the second free layer part

    摘要翻译： MRAM单元分成两部分形成。 使用包括被钉扎层，隧道势垒层和第一自由层部分的第一部分来读取存储的信息位的值。 第二部分包括其上写入和存储信息的第二自由层部分。 第二自由层部分形成有高纵横比的横截面，其使得其具有强烈的磁性各向异性，并使其能够通过静磁相互作用耦合到相对各向同性的第一自由层。 这种相互作用使第一自由层部分的磁化方向与第二自由层部分的磁化方向相反。 第一自由层部分相对于其相邻被钉扎层的磁取向确定第一单元部分的电阻状态，并且可以通过使电流通过第一单元部分来读取该电阻状态。 因此，实际上，第一单元部分成为用于第二自由层部分的磁化取向的遥感装置

    Method of fabricating contact pad for magnetic random access memory
    188.
    发明授权
    Method of fabricating contact pad for magnetic random access memory 有权
    制造磁性随机存取存储器接触焊盘的方法

    公开(公告)号：US07122386B1

    公开(公告)日：2006-10-17

    申请号：US11231674

    申请日：2005-09-21

    申请人： Chyu-Jiuh Torng ,  Tom Zhong ,  Wei Cao ,  Po-Kang Wang

    发明人： Chyu-Jiuh Torng ,  Tom Zhong ,  Wei Cao ,  Po-Kang Wang

    IPC分类号： H01L21/00

    CPC分类号： H01L43/12 ,  H01L27/222

    摘要： A method of forming a Cu—Cu junction between a word line pad (WLP) and bit line (BL) contact is described. An opening above a WL contact is formed in a first SiNx layer on a substrate that includes a WLP and word line. After a bottom electrode (BE) layer, MTJ stack, and hard mask are sequentially deposited, an etch forms an MTJ element above the word line. Another etch forms a BE and exposes the first SiNx layer above the WLP and bond pad (BP). An MTJ ILD layer is deposited and planarized followed by deposition of a second SiNx layer and BL ILD layer. Trenches are formed in the BL ILD layer and second SiNx layer above the WLP, hard mask and BP. After vias are formed in the MTJ ILD and first SiNx layers above the WLP and BP, Cu deposition follows to form dual damascene BL contacts.

    摘要翻译： 描述了在字线焊盘（WLP）和位线（BL）触点之间形成Cu-Cu结的方法。 在包括WLP和字线的衬底上的第一SiN x层中形成WL触点上方的开口。 在底电极（BE）层，MTJ叠层和硬掩模之后，顺序沉积，蚀刻在字线之上形成MTJ元件。 另一蚀刻形成BE，并使WLP和接合焊盘（BP）上方的第一SiN x层暴露。 沉积MTJ ILD层并平坦化，随后沉积第二SiN x层和BL ILD层。 沟槽形成在WLP，硬掩模和BP之上的BL ILD层和第二SiN x x层中。 在WLP和BP上方的MTJ ILD和第一SiN x x层中形成通孔之后，随后进行Cu沉积以形成双镶嵌BL触点。

    Shared bit line SMT MRAM array with shunting transistors between bit lines
    189.
    发明授权
    Shared bit line SMT MRAM array with shunting transistors between bit lines 有权
    共享位线SMT MRAM阵列，在位线之间分流晶体管

    公开(公告)号：US08654577B2

    公开(公告)日：2014-02-18

    申请号：US13887291

    申请日：2013-05-04

    申请人： MagIC Technologies, Inc. ,  International Business Machines Corporation

    发明人： Hsu-Kai Yang ,  Yutaka Nakamura ,  John Debrosse

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1653 ,  G11C7/18 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1675

    摘要： An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.

    摘要翻译： SMT MRAM单元格的行和列阵列具有与其相邻列之一相关联的每个列。 列的每个SMT MRAM单元连接到真数据位线，并且相关联的列对的每个SMT MRAM单元连接到共享补码数据位线。 分流开关装置连接在每个真实数据位线和共享补码数据位线之间，用于选择性地将一条真实数据位线连接到共享补码数据位线，以有效地减小补码数据位线的电阻， 以消除SMT MRAM单元的相邻非选择列中的程序干扰效应。