公开(公告)号：US10191867B1

公开(公告)日：2019-01-29

申请号：US15256583

申请日：2016-09-04

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F13/14 ,  G06F13/16 ,  G06F9/4401 ,  G06F9/44

Abstract: A multiprocessor system includes several processors, a Shared Local Memory (SLMEM), and an interface circuit for interfacing the system to an external posted transaction bus. Each processor has the same address map. Each fetches instructions from SLMEM, and accesses data from/to SLMEM. A processor can initiate a read transaction on the posted transaction bus by doing an AHB-S bus write to a particular address. The AHB-S write determines the type of transaction initiated and also specifies an address in a shared memory in the interface circuit. The interface circuit uses information from the AHB-S write to generate a command of the correct format. The interface circuit outputs the command onto the posted transaction bus, and then receives read data back from the posted transaction bus, and then puts the read data into the shared memory at the address specified by the processor in the original AHB-S bus write.

公开(公告)号：US10044619B1

公开(公告)日：2018-08-07

申请号：US14587513

申请日：2014-12-31

Applicant: Netronome Systems, Inc.

Inventor： Johann Heinrich Tönsing ,  Roelof Nico DuToit ,  Gysbert Floris van Beek Van Leeuwen ,  Jan Neil Viljoen ,  David Wells ,  Leon Johannes Brits ,  Jan Christoffel DuToit

IPC: H04L12/28 ,  H04L12/56 ,  H04L12/801 ,  H04L12/891 ,  H04L12/851 ,  H04L12/813

Abstract: A system and method for handling a digital electronic flow between a first and second entity in which a flow policy is determined that is to be applied to the flow and the flow is then directed along a path in accordance with the policy. An ID is supplied for each flow and a tag associated with each flow which indicates the policy to be applied to its associated flow. Flows are also associated with one another, with associated flows having associated policies. In particular the flow may be processed or forwarded. The path may include a graph structure and virtual applications.

公开(公告)号：US10009270B1

公开(公告)日：2018-06-26

申请号：US14634844

申请日：2015-03-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/741 ,  H04L12/947

CPC classification number: H04L45/745 ,  H04L45/54 ,  H04L49/25

Abstract: A Software-Defined Networking (SDN) switch includes external network ports for receiving external network traffic onto the SDN switch, external network ports for transmitting external network traffic out of the SDN switch, a first Network Flow Switch (NFX) integrated circuit that has multiple network ports and that maintains a first flow table, another Network Flow Switch (NFX) integrated circuit that has multiple network ports and that maintains a second flow table, a Network Flow Processor (NFP) circuit that maintains a third flow table, and a controller processor circuit that maintains a fourth flow table. The controller processor circuit is coupled by a serial bus to the NFP circuit but is not directly coupled by any network port to either the NFP circuit nor the first NFX integrated circuit nor the second NFX integrated circuit.

公开(公告)号：US09998374B1

公开(公告)日：2018-06-12

申请号：US14634845

申请日：2015-03-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/741 ,  H04L12/947 ,  H04L12/931

CPC classification number: H04L45/745 ,  H04L45/54 ,  H04L49/25 ,  H04L49/35

Abstract: A method involves a Software-Defined Networking (SDN) switch that includes multiple Network Flow Switch (NFX) integrated circuits, a Network Flow Processor (NFP) circuit, and a controller processor. The controller processor is coupled to the NFP circuit by a serial bus. A flow table is maintained on each of the NFX integrated circuits. A SDN flow table is maintained on the NFP circuit. A copy of each of the flow tables is maintained on the NFP circuit. Another SDN flow table is maintained on the controller processor. A SDN protocol stack is executed on the controller processor. A SDN protocol message is received onto the SDN switch via one of the NFX integrated circuits. The SDN protocol message is communicated across a network link to the NFP circuit, and across the serial bus from the NFP circuit to the controller processor such that the SDN protocol message is received and processed by the SDN protocol stack executing on the controller processor.

公开(公告)号：US09971720B1

公开(公告)日：2018-05-15

申请号：US14724820

申请日：2015-05-29

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos ,  Ronald N. Fortino

IPC: G06F13/40

CPC classification number: G06F13/4022 ,  G06F13/00 ,  H04L47/39 ,  H04L49/901

Abstract: An island-based integrated circuit includes a configurable mesh data bus. The data bus includes four meshes. Each mesh includes, for each island, a crossbar switch and radiating half links. The half links of adjacent islands align to form links between crossbar switches. A link is implemented as two distributed credit FIFOs. In one direction, a link portion involves a FIFO associated with an output port of a first island, a first chain of registers, and a second FIFO associated with an input port of a second island. When a transaction value passes through the FIFO and through the crossbar switch of the second island, an arbiter in the crossbar switch returns a taken signal. The taken signal passes back through a second chain of registers to a credit count circuit in the first island. The credit count circuit maintains a credit count value for the distributed credit FIFO.

公开(公告)号：US09929933B1

公开(公告)日：2018-03-27

申请号：US14841717

申请日：2015-09-01

Applicant: Netronome Systems, Inc.

Inventor： Nicolaas J. Viljoen

IPC: H04B10/00 ,  H04L12/751 ,  H04B10/27 ,  H04L29/06 ,  H04J14/00

CPC classification number: H04L45/02 ,  H04B10/27 ,  H04L43/026 ,  H04L43/0876 ,  H04L43/16

Abstract: A flow of packets is communicated through a data center. The data center includes multiple racks, where each rack includes multiple network devices. A group of packets of the flow is received onto an integrated circuit located in one of the network devices. The integrated circuit includes a neural network and a flow table. The neural network analyzes the group of packets and in response determines if it is likely that the flow has a particular characteristic. The neural network outputs a neural network output value that indicates if it is likely that the flow has a particular characteristic. The neural network output value, or a value derived from it, is included in a flow entry in the flow table on the integrated circuit. Packets of the flow subsequently received onto the integrated circuit are routed or otherwise processed according to the flow entry associated with the flow.

公开(公告)号：US09912591B1

公开(公告)日：2018-03-06

申请号：US14726421

申请日：2015-05-29

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/741 ,  H04L29/06

CPC classification number: H04L45/745 ,  G06F9/445 ,  H04L67/02 ,  H04L69/22

Abstract: An exact-match flow table structure of an integrated circuit stores flow entries. Each flow entry includes a Flow Id and an action value. Each Flow Id is a multi-bit digital value that uniquely identifies a flow. A Flow Id does not include any wildcard indictor. The flow table structure cannot and does not store an indicator that any particular part of a packet should be matched against any part of a Flow Id. In one example, a packet is received onto the integrated circuit. A Flow Id is generated from the packet. If the flow table structure determines that the Flow Id is a bit-by-bit exact-match of any Flow Id of any stored flow entry, then the packet is handled according to the action value of the flow entry. If, on the other hand, there is not exact-match, then a miss indication is output from the integrated circuit.

公开(公告)号：US09887918B1

公开(公告)日：2018-02-06

申请号：US14530762

申请日：2014-11-02

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/30 ,  H04L12/741

CPC classification number: H04L49/90

Abstract: A multi-processor includes a pool of processors and a common packet buffer memory. Bytes of packet data of a packet are stored in the packet buffer memory. Each of the processors has an intelligent packet data register file. One processor is tasked with processing the packet data, and its packet data register file caches a subset of the bytes of packet data. Some instructions when executed require that the packet data register file supply the execute stage of the processor with certain bytes of the packet data. If during instruction execution the intelligent packet data register file determines that it does not store some of the necessary bytes, then the register file asserts a stall signal thereby stalling the processor, and retrieves the bytes from the packet buffer memory, and then supplies the retrieved bytes to the execute stage, and de-asserts the stall signal to unstall the processor.

公开(公告)号：US09854072B1

公开(公告)日：2017-12-26

申请号：US14818070

申请日：2015-08-04

Applicant: Netronome Systems, Inc.

Inventor： Chirag P. Patel ,  Gavin J. Stark

IPC: H04L29/06 ,  H04L12/935

CPC classification number: H04L69/22 ,  G06F9/00 ,  G06F9/30018 ,  G06F9/3867 ,  H04L49/3063 ,  H04L69/04

Abstract: An egress packet modifier includes a script parser and a pipeline of processing stages. Rather than performing egress modifications using a processor that fetches and decodes and executes instructions in a classic processor fashion, and rather than storing a packet in memory and reading it out and modifying it and writing it back, the packet modifier pipeline processes the packet by passing parts of the packet through the pipeline. A processor identifies particular egress modifications to be performed by placing a script code at the beginning of the packet. The script parser then uses the code to identify a specific script of opcodes, where each opcode defines a modification. As a part passes through a stage, the stage can carry out the modification of such an opcode. As realized using current semiconductor fabrication process, the packet modifier can modify 200M packets/second at a sustained rate of up to 100 gigabits/second.

公开(公告)号：US09804976B1

公开(公告)日：2017-10-31

申请号：US14841300

申请日：2015-08-31

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Johann H. Tönsing

IPC: G06F12/14 ,  G06F9/46

CPC classification number: G06F12/1466 ,  G06F9/467 ,  G06F17/30 ,  G06F17/30362 ,  G06F2212/1052

Abstract: A transactional memory (TM) receives an Atomic Look-up, Add and Lock (ALAL) command across a bus from a client. The command includes a first value. The TM pulls a second value. The TM uses the first value to read a set of memory locations, and determines if any of the locations contains the second value. If no location contains the second value, then the TM locks a vacant location, adds the second value to the vacant location, and sends a result to the client. If a location contains the second value and it is not locked, then the TM locks the location and returns a result to the client. If a location contains the second value and it is locked, then the TM returns a result to the client. Each location has an associated data structure. Setting the lock field of a location locks access to its associated data structure.