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    CMOS DEVICE AND METHOD OF MANUFACTURING SAME
    11.
    发明申请
    CMOS DEVICE AND METHOD OF MANUFACTURING SAME 有权
    CMOS器件及其制造方法

    公开(公告)号：US20090321838A1

    公开(公告)日：2009-12-31

    申请号：US12215989

    申请日：2008-06-30

    Applicant: Bernhard Sell ,  Anand Murthy ,  Mark Liu ,  Daniel B. Aubertine

    Inventor： Bernhard Sell ,  Anand Murthy ,  Mark Liu ,  Daniel B. Aubertine

    IPC: H01L29/423 ,  H01L21/8238

    CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L29/66628 ,  H01L29/7834

    Abstract: A CMOS device includes NMOS (110) and PMOS (130) transistors, each of which include a gate electrode (111, 131) and a gate insulator (112, 132) that defines a gate insulator plane (150, 170). The transistors each further include source/drain regions (113/114, 133/134) having a first portion (115, 135) below the gate insulator plane and a second portion (116, 136) above the gate insulator plane, and an electrically insulating material (117). The NMOS transistor further includes a blocking layer (121) having a portion (122) between the gate electrode and a source contact (118) and a portion (123) between the gate electrode and a drain contact (119). The PMOS transistor further includes a blocking layer (141) having a portion (142) between the source region and the insulating material and a portion (143) between the drain region and the insulating material.

    Abstract translation: CMOS器件包括NMOS（110）和PMOS（130）晶体管，每个晶体管包括限定栅极绝缘体平面（150,170）的栅电极（111,131）和栅极绝缘体（112,132）。 晶体管每个还包括具有栅极绝缘体平面下方的第一部分（115,135）和栅极绝缘体平面上方的第二部分（116,136）的源/漏区（113/114,133 / 134） 绝缘材料（117）。 NMOS晶体管还包括阻挡层（121），其具有在栅电极和源极触点（118）之间的部分（122）和栅极电极和漏极触点（119）之间的部分（123）。 所述PMOS晶体管还包括阻挡层（141），所述阻挡层（141）具有在所述源极区域和所述绝缘材料之间的部分（142）以及所述漏极区域和所述绝缘材料之间的部分（143）。

    Systems And Methods To Increase Uniaxial Compressive Stress In Tri-Gate Transistors
    12.
    发明申请
    Systems And Methods To Increase Uniaxial Compressive Stress In Tri-Gate Transistors 审中-公开
    在三栅晶体管中提高单轴压缩应力的系统和方法

    公开(公告)号：US20090152589A1

    公开(公告)日：2009-06-18

    申请号：US11958275

    申请日：2007-12-17

    Applicant: Titash Rakshit ,  Martin D. Giles ,  Tahir Ghani ,  Anand Murthy ,  Stephen M. Cea

    Inventor： Titash Rakshit ,  Martin D. Giles ,  Tahir Ghani ,  Anand Murthy ,  Stephen M. Cea

    IPC: H01L29/778 ,  H01L21/8234

    CPC classification number: H01L21/26506 ,  H01L21/823437 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

    Abstract: A transistor structure that increases uniaxial compressive stress on the channel region of a tri-gate transistor comprises at least two semiconductor bodies formed on a substrate, each semiconductor body having a pair of laterally opposite sidewalls and a top surface, a common source region formed on one end of the semiconductor bodies, wherein the common source region is coupled to all of the at least two semiconductor bodies, a common drain region formed on another end of the semiconductor bodies, wherein the common drain region is coupled to all of the at least two semiconductor bodies, and a common gate electrode formed over the at least two semiconductor bodies, wherein the common gate electrode provides a gate electrode for each of the at least two semiconductor bodies and wherein the common gate electrode has a pair of laterally opposite sidewalls that are substantially perpendicular to the sidewalls of the semiconductor bodies.

    Abstract translation: 增加三栅极晶体管的沟道区上的单轴压应力的晶体管结构包括形成在衬底上的至少两个半导体本体，每个半导体本体具有一对横向相对的侧壁和顶表面，共同源极区形成在 所述半导体主体的一端，其中所述公共源极区域耦合到所述至少两个半导体主体中的所有半导体主体，形成在所述半导体主体的另一端上的公共漏极区域，其中，所述公共漏极区域至少与所述半导体主体 两个半导体主体和形成在所述至少两个半导体主体上的公共栅电极，其中所述公共栅电极为所述至少两个半导体主体中的每一个提供栅电极，并且其中所述公共栅极具有一对横向相对的侧壁， 基本上垂直于半导体主体的侧壁。

    Method of fabricating a field effect transistor structure with abrupt source/drain junctions
    16.
    发明申请
    Method of fabricating a field effect transistor structure with abrupt source/drain junctions 有权
    制造具有突然的源极/漏极结的场效应晶体管结构的方法

    公开(公告)号：US20060220153A1

    公开(公告)日：2006-10-05

    申请号：US11437569

    申请日：2006-05-19

    Applicant: Anand Murthy ,  Robert Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

    Inventor： Anand Murthy ,  Robert Chau ,  Patrick Morrow ,  Chia-Hong Jan ,  Paul Packan

    IPC: H01L29/76

    CPC classification number: H01L29/66636 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/2022 ,  H01L29/0646 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41783 ,  H01L29/4925 ,  H01L29/66477 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

    Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

    Abstract translation: 体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。 形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。 凹部包括在栅极结构的一部分下面的横向延伸的区域。 这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。 在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。 以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。 替代实施例可以用单导电类型的后填充凹槽来实现。

    Method for forming an integrated circuit
    17.
    发明申请
    Method for forming an integrated circuit 有权
    集成电路形成方法

    公开(公告)号：US20060131665A1

    公开(公告)日：2006-06-22

    申请号：US11336160

    申请日：2006-01-20

    Applicant: Anand Murthy ,  Glenn Glass ,  Andrew Westmeyer ,  Michael Hattendorf ,  Tahir Ghani

    Inventor： Anand Murthy ,  Glenn Glass ,  Andrew Westmeyer ,  Michael Hattendorf ,  Tahir Ghani

    IPC: H01L29/76

    CPC classification number: H01L29/7834 ,  H01L29/665 ,  H01L29/66636

    Abstract: A method is described for manufacturing an n-MOS semiconductor transistor. Recesses are formed in a semiconductor substrate adjacent a gate electrode structure. Silicon is embedded in the recesses via a selective epitaxial growth process. The epitaxial silicon is in-situ alloyed with substitutional carbon and in-situ doped with phosphorus. The silicon-carbon alloy generates a uniaxial tensile strain in the channel region between the source and drain, thereby increasing electron channel mobility and the transistor's drive current. The silicon-carbon alloy decreases external resistances by reducing contact resistance between source/drain and silicide regions and by reducing phosphorous diffusivity, thereby permitting closer placement of the transistor's source/drain and channel regions.

    Abstract translation: 描述了制造n-MOS半导体晶体管的方法。 在与栅电极结构相邻的半导体衬底中形成凹部。 硅通过选择性外延生长工艺嵌入凹槽中。 外延硅与替代原位合金化并原位掺磷。 硅碳合金在源极和漏极之间的沟道区域中产生单轴拉伸应变，从而增加电子通道迁移率和晶体管的驱动电流。 硅碳合金通过降低源极/漏极和硅化物区域之间的接触电阻并减少磷扩散率来降低外部电阻，从而允许晶体管的源极/漏极和沟道区域更靠近放置。

    Methods for selective deposition to improve selectivity
    19.
    发明申请
    Methods for selective deposition to improve selectivity 审中-公开
    用于选择性沉积以提高选择性的方法

    公开(公告)号：US20060057809A1

    公开(公告)日：2006-03-16

    申请号：US11270933

    申请日：2005-11-10

    Applicant: Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

    Inventor： Anand Murthy ,  Nayanee Gupta ,  Chris Auth ,  Glenn Glass

    IPC: H01L21/336

    CPC classification number: H01L29/66636 ,  H01L21/823418

    Abstract: Methods and associated apparatus of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising a region of higher active area density comprising source and drain recesses and a region of lower active area density comprising source and drain recesses, wherein the region of lower active area density further comprises dummy recesses, and selectively depositing a silicon alloy layer in the source, drain and dummy recesses to enhance the selectivity and uniformity of the silicon alloy deposition.

    Abstract translation: 描述形成微电子结构的方法和相关装置。 那些方法包括提供一种衬底，其包括具有源极和漏极凹部的较高有源面积密度的区域和包括源极和漏极凹陷的较低有源面积密度的区域，其中较低有源面积密度的区域还包括虚设凹槽，并且选择性地沉积 源极，漏极和虚拟凹槽中的硅合金层，以增强硅合金沉积的选择性和均匀性。

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