公开(公告)号：US5710869A

公开(公告)日：1998-01-20

申请号：US485337

申请日：1995-06-07

Applicant: Catherine Godefroy ,  Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

Inventor： Catherine Godefroy ,  Andre Steimle ,  Pascal Tannhof ,  Guy Paillet

IPC: G06F15/18 ,  G06N3/00 ,  G06N3/04 ,  G06N3/06 ,  G06N3/063 ,  G06F15/00

CPC classification number: G06N3/063

Abstract: Each daisy chain circuit is serially connected to the two adjacent neuron circuits, so that all the neuron circuits form a chain. The daisy chain circuit distinguishes between the two possible states of the neuron circuit (engaged or free) and identifies the first free "or ready to learn" neuron circuit in the chain, based on the respective values of the input (DCI) and output (DCO) signals of the daisy chain circuit. The ready to learn neuron circuit is the only neuron circuit of the neural network having daisy chain input and output signals complementary to each other. The daisy chain circuit includes a 1-bit register (601) controlled by a store enable signal (ST) which is active at initialization or, during the learning phase when a new neuron circuit is engaged. At initialization, all the Daisy registers of the chain are forced to a first logic value. The DCI input of the first daisy chain circuit in the chain is connected to a second logic value, such that after initialization, it is the ready to learn neuron circuit. In the learning phase, the ready to learn neuron's 1-bit daisy register contents are set to the second logic value by the store enable signal, it is said "engaged". As neurons are engaged, each subsequent neuron circuit in the chain then becomes the next ready to learn neuron circuit.

Abstract translation: 每个菊花链电路串联连接到两个相邻的神经元电路，使得所有的神经元电路形成链。 菊花链电路基于输入（DCI）和输出（DCI）的相应值来区分神经元电路的两种可能状态（被接合或自由）并且识别链中的第一个“准备学习”神经元电路 DCO）信号。 准备学习神经元电路是具有菊花链输入和输出信号彼此互补的神经网络的唯一神经元电路。 菊花链电路包括由初始化时有效的存储使能信号（ST）控制的1位寄存器（601），或者在新的神经元电路被接合时的学习阶段。 在初始化时，链的所有Daisy寄存器都被强制为第一个逻辑值。 链中第一个菊花链电路的DCI输入连接到第二个逻辑值，这样在初始化之后就可以学习神经元电路了。 在学习阶段，准备学习神经元的1位菊花寄存器内容通过存储使能信号设置为第二个逻辑值，它被称为“被接合”。 随着神经元的啮合，链中随后的每个神经元电路就成为下一个准备学习神经元电路的准备。

公开(公告)号：US20070011534A1

公开(公告)日：2007-01-11

申请号：US11164690

申请日：2005-12-01

Applicant: Gerard Boudon ,  Didier Malcavet ,  David Pereira ,  Andre Steimle

Inventor： Gerard Boudon ,  Didier Malcavet ,  David Pereira ,  Andre Steimle

IPC: G01R31/28

CPC classification number: G01R31/3171

Abstract: A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator compares the first data set with a second data set generated by the receiver LFSR and adjusts the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract translation: 一种自同步数据总线分析器，包括发生器LFSR，接收器LFSR和比较器，其中发生器LFSR产生通过数据总线传送到比较器的第一数据组; 并且其中所述比较器将所述第一数据集与由所述接收器LFSR生成的第二数据集进行比较，并且调整所述接收器LFSR，直到所述第二数据集与所述第一数据集基本相同。

公开(公告)号：US06502083B1

公开(公告)日：2002-12-31

申请号：US09470458

申请日：1999-12-22

Applicant: Didier Louis ,  Pascal Tannhof ,  Andre Steimle

Inventor： Didier Louis ,  Pascal Tannhof ,  Andre Steimle

IPC: G06N306

CPC classification number: G06K9/6276 ,  G06N3/063

Abstract: The improved neuron is connected to input buses which transport input data and control signals. It basically consists of a computation block, a register block, an evaluation block and a daisy chain block. All these blocks, except the computation block substantially have a symmetric construction. Registers are used to store data: the local norm and context, the distance, the AIF value and the category. The improved neuron further needs some R/W memory capacity which may be placed either in the neuron or outside. The evaluation circuit is connected to an output bus to generate global signals thereon. The daisy chain block allows to chain the improved neuron with others to form an artificial neural network (ANN). The improved neuron may work either as a single neuron (single mode) or as two independent neurons (dual mode). In the latter case, the computation block, which is common to the two dual neurons, must operate sequentially to service one neuron after the other. The selection between the two modes (single/dual) is made by the user which stores a specific logic value in a dedicated register of the control logic circuitry in each improved neuron.

Abstract translation: 改进的神经元连接到传输输入数据和控制信号的输入总线。 它基本上由计算块，寄存器块，评估块和菊花链块组成。 除了计算块之外，所有这些块基本上具有对称结构。 寄存器用于存储数据：本地规范和上下文，距离，AIF值和类别。 改进的神经元还需要一些R / W记忆容量，这可能被放置在神经元或外部。 评估电路连接到输出总线，以在其上产生全局信号。 菊花链块允许与其他人链接改进的神经元以形成人造神经网络（ANN）。 改善的神经元可以作为单个神经元（单个模式）或两个独立的神经元（双模式）起作用。 在后一种情况下，两个双重神经元共同的计算块必须依次操作，以便在一个神经元之后进行服务。 两种模式之间的选择（单/双）由在每个改进的神经元中的控制逻辑电路的专用寄存器中存储特定逻辑值的用户进行。

公开(公告)号：US5452241A

公开(公告)日：1995-09-19

申请号：US209589

申请日：1994-03-14

Applicant: Bernard Desrosiers ,  Louis Didier ,  Didier Pinchon ,  Andre Steimle

Inventor： Bernard Desrosiers ,  Louis Didier ,  Didier Pinchon ,  Andre Steimle

IPC: G06F7/38 ,  G06F7/483 ,  G06F7/487 ,  G06F7/52 ,  G06F7/527 ,  G06F7/533 ,  G06F7/548 ,  G06F17/10 ,  G06F7/00

CPC classification number: G06F7/4876 ,  G06F7/548 ,  G06F7/49942

Abstract: A method for approximating mathematical functions using polynomial expansions is implemented in a numeric processing system. A partial remainder operation is set forth for high accuracy reduction of polynomials whose arguments are greater than pi/4. The method may be practiced in a processor having a bus of approximately half the width of the precision of the desired result. Temporary registers are utilized for the storage of intermediate results. Full bus width accuracy is obtained through successive half bus width operations.

Abstract translation: 在数字处理系统中实现使用多项式扩展近似数学函数的方法。 为了高精度降低参数大于pi / 4的多项式，提出了部分余数运算。 该方法可以在具有所需结果的精度的大约一半宽度的总线的处理器中实现。 临时寄存器用于存储中间结果。 通过连续的半总线宽度操作获得完整的总线宽度精度。

公开(公告)号：US5337265A

公开(公告)日：1994-08-09

申请号：US981031

申请日：1992-11-24

Applicant: Bernard Desrosiers ,  Didier Louis ,  Andre Steimle

Inventor： Bernard Desrosiers ,  Didier Louis ,  Andre Steimle

IPC: G06F7/485 ,  G06F7/50

CPC classification number: G06F7/485

Abstract: A numeric data coprocessor having an execution unit adapted to efficiently execute addition/subtraction operations on floating-point numbers in compliance with the IEEE standard 754. The mantissa adder carry out bit resulting from the operation on two operands X and Y is directly concatenated with the mantissa adder result in the mantissa output register to be the MSB thereof. Simultaneously, a 1 is added to the exponent of operand X or Y with the highest value. The final result is found after normalizing, regardless of whether the carry out bit is 1 or 0.In its hardware embodiment, taking for example the 80-bit double extended precision IEEE format, the mantissa output register has 68 positions. The 68th supplementary position is fed by the carry out bit generated by the mantissa adder at the "carry out" output. The "Force Carry" input of the exponent adder is activated by the control logic circuitry to add a 1 to the operand exponent with the highest value.

Abstract translation: 一种具有执行单元的数字数据协处理器，其适于根据IEEE标准754有效地对浮点数执行加法/减法运算。尾数加法器执行由两个操作数X和Y上的操作产生的位直接连接到 尾数加法器将尾数输出寄存器作为其MSB。 同时，对于具有最高值的操作数X或Y的指数加1。 无论进位位是1还是0，都在归一化后找到最终结果。在其硬件实施例中，例如采用80位双倍扩展精度IEEE格式，尾数输出寄存器具有68个位置。 第68个补充位置由在“进位输出”输出处由尾数加法器产生的进位位进给。 指数加法器的“强制进位”输入由控制逻辑电路激活，以将最大值的操作数指数加1。