Method and apparatus for updating system software for a plurality of
data processing units in a communication network
    11.
    发明授权
    Method and apparatus for updating system software for a plurality of data processing units in a communication network 失效
    用于更新通信网络中的多个数据处理单元的系统软件的方法和装置

    公开(公告)号:US5008814A

    公开(公告)日:1991-04-16

    申请号:US232293

    申请日:1988-08-15

    Applicant: Ashish Mathur

    Inventor: Ashish Mathur

    CPC classification number: G06F8/65

    Abstract: In maintaining a communication network of processing units distributed in multiple nodes linked by communication channels, system software in a plurality of data processing units is updated by first installing the updated software in a first node. The updated software is transmitted through the network to other nodes. A trial use of the updated software is initiated in the nodes. If failures of the updated software are detected in a node, that node will be restored to the original software version. If the trial use of the updated software is completed successfully in a node, the updated version will be installed as a preferred operational version in the node. a

    Abstract translation: 在维护分布在由通信信道链接的多个节点中的处理单元的通信网络中,通过首先在第一节点中安装更新的软件来更新多个数据处理单元中的系统软件。 更新的软件通过网络传输到其他节点。 在节点中启动更新软件的试用。 如果在节点中检测到更新的软件故障,则该节点将恢复到原始软件版本。 如果在节点中成功完成更新软件的试用,则更新的版本将作为节点中的首选操作版本进行安装。

    Method and system for estimating power consumption of integrated circuit design
    12.
    发明授权
    Method and system for estimating power consumption of integrated circuit design 有权
    集成电路设计功耗估算方法及系统

    公开(公告)号:US07971082B2

    公开(公告)日:2011-06-28

    申请号:US12013478

    申请日:2008-01-14

    CPC classification number: G06F9/3869

    Abstract: A method and system for estimating power consumption for at least one Intellectual Property (IP) block in an integrated circuit (IC) design includes identifying at least one port in the at least one IP block. The at least one port is associated with at least one operation. A sequence of micro-operations of the at least one operation is identified. The sequence of micro-operations constitutes an operation pipeline. A set of micro-operations per cycle in the operation pipeline and energy per cycle of each cycle of the operation pipeline, based on the set of micro-operations per cycle by using one or more of, an idle energy value, a micro-operation isolated energy (MIE) value, an overlap energy (OE) value, and a micro-operation overlap energy (MOE) value, are determined. Then the power consumption of the at least one IP block is determined using the energy per cycle of each cycle of the operation pipeline.

    Abstract translation: 用于估计集成电路(IC)设计中的至少一个知识产权(IP)块的功率消耗的方法和系统包括识别所述至少一个IP块中的至少一个端口。 至少一个端口与至少一个操作相关联。 识别至少一个操作的一系列微操作。 微操作的顺序构成操作流程。 基于通过使用空闲能量值,微操作的每个周期的微操作的集合,在操作流水线中的每个周期的一组微操作和每个操作流水线的每个周期的每个周期的能量 分离能量(MIE)值,重叠能量(OE)值和微操作重叠能量(MOE)值。 然后,使用运行管线的每个循环的每循环的能量确定至少一个IP块的功率消耗。

    METHOD AND SYSTEM FOR ESTIMATING POWER CONSUMPTION OF INTEGRATED CIRCUIT DESIGN
    13.
    发明申请
    METHOD AND SYSTEM FOR ESTIMATING POWER CONSUMPTION OF INTEGRATED CIRCUIT DESIGN 有权
    用于估计集成电路设计功耗的方法和系统

    公开(公告)号:US20080184049A1

    公开(公告)日:2008-07-31

    申请号:US12013478

    申请日:2008-01-14

    CPC classification number: G06F9/3869

    Abstract: A method and system for estimating power consumption for at least one Intellectual Property (IP) block in an integrated circuit (IC) design includes identifying at least one port in the at least one IP block. The at least one port is associated with at least one operation. A sequence of micro-operations of the at least one operation is identified. The sequence of micro-operations constitutes an operation pipeline. A set of micro-operations per cycle in the operation pipeline and energy per cycle of each cycle of the operation pipeline, based on the set of micro-operations per cycle by using one or more of, an idle energy value, a micro-operation isolated energy (MIE) value, an overlap energy (OE) value, and a micro-operation overlap energy (MOE) value, are determined. Then the power consumption of the at least one IP block is determined using the energy per cycle of each cycle of the operation pipeline.

    Abstract translation: 用于估计集成电路(IC)设计中的至少一个知识产权(IP)块的功率消耗的方法和系统包括识别所述至少一个IP块中的至少一个端口。 至少一个端口与至少一个操作相关联。 识别至少一个操作的一系列微操作。 微操作的顺序构成操作流程。 基于通过使用空闲能量值,微操作的每个周期的微操作的集合,在操作流水线中的每个周期的一组微操作和每个操作流水线的每个周期的每个周期的能量 分离能量(MIE)值,重叠能量(OE)值和微操作重叠能量(MOE)值。 然后,使用运行管线的每个循环的每循环的能量确定至少一个IP块的功率消耗。

    METHOD FOR ESTIMATING PROCESSOR ENERGY USAGE
    14.
    发明申请
    METHOD FOR ESTIMATING PROCESSOR ENERGY USAGE 有权
    估算处理器能量使用的方法

    公开(公告)号:US20070136720A1

    公开(公告)日:2007-06-14

    申请号:US11609102

    申请日:2006-12-11

    Abstract: A method for estimating energy usage of a program code executed by a very long instruction word (VLIW) processor. The program code includes multiple instructions, which are organized as groups referred to as execution sets. The instructions of an execution set are executed simultaneously. A no operation (NOP) energy and incremental instruction energy for each execution set of the program code are determined to compute a base energy of each execution set. An inter-execution set energy of each execution set is then computed. The estimated energy usage of each execution set is determined by adding the corresponding inter-execution set energies to the base energies. A stall energy consumed on account of executing the program code is then computed. Finally, the estimated energy usage of the program code is determined by adding the stall energy to the determined energies of all the execution sets.

    Abstract translation: 一种用于估计由非常长的指令字(VLIW)处理器执行的程序代码的能量使用的方法。 程序代码包括多个指令,它们被组织为被称为执行集的组。 执行集的指令同时执行。 确定程序代码的每个执行集合的无操作(NOP)能量和增量指令能量以计算每个执行集的基本能量。 然后计算每个执行集合的执行间集合能量。 每个执行集合的估计能量使用通过将相应的执行中的集合能量相加到基本能量来确定。 然后计算由于执行程序代码而消耗的失速能量。 最后,通过将停顿能量加到所有执行集合的确定的能量来确定程序代码的估计能量使用。

    Recyclable thermoplastic moldable nonwoven liner for office partition and method for its manufacture
    15.
    发明授权
    Recyclable thermoplastic moldable nonwoven liner for office partition and method for its manufacture 失效
    用于办公室分区的可回收热塑性可塑性非织造衬里及其制造方法

    公开(公告)号:US06517676B1

    公开(公告)日:2003-02-11

    申请号:US09478826

    申请日:2000-01-06

    Applicant: Ashish Mathur

    Inventor: Ashish Mathur

    CPC classification number: D21H13/24 D21H15/10 D21H17/35 D21H25/06

    Abstract: A rigid thermoformable recyclable nonwoven liner material is formed by a wet process on a papermaking machine. The rigid thermoformable nonwoven liner material is intended to be laminated to a woven fabric and then thermomolded around a wooden panel to form an office partition. The wet-laying process may consist entirely of conventional steps. The fiber furnish includes polyester matrix fibers and co-polyester/polyester bicomponent binder fibers. The web of fibers coming off the papermaking machine is passed through a foam press, which applies a water-based medium having polyvinyl chloride binder dispersed therein. The web is dried, treated again with a water-based medium having polyvinyl chloride binder dispersed therein and then dried again. The final product can be molded in a wide range of temperatures ranging from 225° to 300° F.

    Abstract translation: 通过湿法在造纸机上形成刚性的可热成形的可再循环的非织造衬里材料。 刚性可热成形的非织造衬里材料旨在层压到机织织物上,然后在木质板周围热成型以形成办公室分区。 湿式铺设过程可能完全由常规步骤组成。 纤维配料包括聚酯基质纤维和共聚酯/聚酯双组分粘合剂纤维。 从造纸机出来的纤维网通过泡沫压榨机,该压榨机应用分散有聚氯乙烯粘合剂的水性介质。 将纸幅干燥,再次用分散有聚氯乙烯粘合剂的水性介质处理,然后再次干燥。 最终产品可以在225°至300°F的宽范围内模制。

    Multi-threaded system for performing atomic binary translations
    16.
    发明授权
    Multi-threaded system for performing atomic binary translations 有权
    用于执行原子二进制翻译的多线程系统

    公开(公告)号:US09053035B1

    公开(公告)日:2015-06-09

    申请号:US14088446

    申请日:2013-11-25

    CPC classification number: G06F9/3004 G06F8/45 G06F8/52 G06F9/45558

    Abstract: A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of a load linked shared memory address of the load linked instruction is the same as the store conditional shared memory address, a reservation flag indicates that the thread has a valid reservation, and the copy of data stored by the load linked instruction is the same as data stored in the store conditional shared memory address.

    Abstract translation: 多线程二进制翻译系统通过线程执行原子操作,这样的操作包括处理加载链接指令和存储条件指令。 存储条件指令仅在满足至少三个条件时更新存储在共享存储器地址中的数据。 条件是:负载链接指令的负载链接共享存储器地址的副本与存储条件共享存储器地址相同,保留标志指示线程具有有效预留,以及负载存储的数据副本 链接指令与存储在存储条件共享存储器地址中的数据相同。

    MULTI-THREADED SYSTEM FOR PERFORMING ATOMIC BINARY TRANSLATIONS
    17.
    发明申请
    MULTI-THREADED SYSTEM FOR PERFORMING ATOMIC BINARY TRANSLATIONS 有权
    用于执行原子二进制翻译的多线程系统

    公开(公告)号:US20150149725A1

    公开(公告)日:2015-05-28

    申请号:US14088446

    申请日:2013-11-25

    CPC classification number: G06F9/3004 G06F8/45 G06F8/52 G06F9/45558

    Abstract: A multi-threaded binary translation system performs atomic operations by a thread, such operations include processing a load linked instruction and a store conditional instruction. The store conditional instruction updates data stored in a shared memory address only when at least three conditions are satisfied. The conditions are: a copy of a load linked shared memory address of the load linked instruction is the same as the store conditional shared memory address, a reservation flag indicates that the thread has a valid reservation, and the copy of data stored by the load linked instruction is the same as data stored in the store conditional shared memory address.

    Abstract translation: 多线程二进制翻译系统通过线程执行原子操作,这样的操作包括处理加载链接指令和存储条件指令。 存储条件指令仅在满足至少三个条件时更新存储在共享存储器地址中的数据。 条件是:负载链接指令的负载链接共享存储器地址的副本与存储条件共享存储器地址相同,保留标志指示线程具有有效预留,以及负载存储的数据副本 链接指令与存储在存储条件共享存储器地址中的数据相同。

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