公开(公告)号：US20130120051A1

公开(公告)日：2013-05-16

申请号：US13737624

申请日：2013-01-09

Applicant: Chiang PU ,  Ming-Chieh HUANG ,  Chan-Hong CHERN

Inventor： Chiang PU ,  Ming-Chieh HUANG ,  Chan-Hong CHERN

IPC: G05F1/10

CPC classification number: G05F1/10 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4065

Abstract: A circuit includes a comparator, a first circuit, and a second circuit. The comparator includes a first input node, a second input node, and an output node. The first circuit is configured to generate a temperature-dependent reference current at the second input node of the comparator. The second circuit is coupled with the second input node of the comparator. The second circuit is configured to increase a voltage level at the second input node of the comparator in response to the temperature-dependent reference current when a signal at the output node of the comparator indicates a first comparison result, and decrease the voltage level at the second input node of the comparator when the signal at the output node of the comparator indicates a second comparison result.

Abstract translation: 电路包括比较器，第一电路和第二电路。 比较器包括第一输入节点，第二输入节点和输出节点。 第一电路被配置为在比较器的第二输入节点处产生与温度相关的参考电流。 第二电路与比较器的第二输入节点耦合。 第二电路被配置为当比较器的输出节点处的信号指示第一比较结果时，响应于温度相关的参考电流来增加比较器的第二输入节点处的电压电平，并且降低电压电平 当比较器的输出节点处的信号指示第二比较结果时，比较器的第二输入节点。

公开(公告)号：US20130106475A1

公开(公告)日：2013-05-02

申请号：US13718235

申请日：2012-12-18

Applicant: Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

Inventor： Chih-Chang LIN ,  Chan-Hong CHERN ,  Steven SWEI ,  Ming-Chieh HUANG ,  Tien-Chun YANG

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/081 ,  H03L7/087

Abstract: A method of operating a charge pump of a phase-lock assistant circuit includes determining a first relative timing relationship of a phase of a data signal to a phase of a first phase clock. A second relative timing relationship of the phase of the data signal to a phase of a second phase clock is determined, and the first and second phase clocks have a 45° phase difference. An up signal and a down signal are generated in response to the first relative timing relationship and the second relative timing relationship. The charge pump circuit is driven according to the up signal and the down signal.

Abstract translation: 操作锁相辅助电路的电荷泵的方法包括确定数据信号的相位与第一相位时钟的相位的第一相对定时关系。 确定数据信号的相位与第二相位时钟的相位的第二相对定时关系，并且第一和第二相位时钟具有45°的相位差。 响应于第一相对定时关系和第二相对定时关系产生升高信号和下降信号。 电荷泵电路根据上升信号和下降信号进行驱动。

公开(公告)号：US20130082754A1

公开(公告)日：2013-04-04

申请号：US13252498

申请日：2011-10-04

Applicant: Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Fu-Lung HSUEH ,  Yuwen SWEI

Inventor： Chan-Hong CHERN ,  Ming-Chieh HUANG ,  Tao Wen CHUNG ,  Chih-Chang LIN ,  Fu-Lung HSUEH ,  Yuwen SWEI

IPC: H03L7/08

CPC classification number: H03L7/102 ,  H03L7/099 ,  H03L2207/06

Abstract: An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.

Abstract translation: 电感 - 电容器锁相环（LCPLL）包括提供输出频率的电感 - 电容压控振荡器（LCVCO）。 校准电路包括两个比较器，并向LCVCO提供粗调信号。 两个比较器分别将环路滤波器信号与第一参考电压和高于第一参考电压的第二参考电压进行比较，以分别提供第一和第二比较器输出。 校准电路能够在电压值中连续调整粗调信号，并根据两个比较器输出调整粗调信号。 环路滤波器向校准电路提供环路滤波器信号，并向LCVCO提供微调信号。 粗调频率范围大于微调频率范围。

公开(公告)号：US08369172B2

公开(公告)日：2013-02-05

申请号：US12844204

申请日：2010-07-27

Applicant: Chiang Pu ,  Ming-Chieh Huang ,  Chan-Hong Chern

Inventor： Chiang Pu ,  Ming-Chieh Huang ,  Chan-Hong Chern

IPC: G11C7/00

CPC classification number: G05F1/10 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4065

Abstract: An integrated circuit includes a capacitor. A switch is electrically coupled with the capacitor in a parallel fashion. A comparator includes a first input node, a second input node, and an output node. The second input node is electrically coupled with a first plate of the capacitor. The output node is electrically coupled with the switch. A transistor is electrically coupled with a second plate of the capacitor. A circuit is electrically coupled with a gate of the transistor. The circuit is configured to provide a bias voltage to the gate of the transistor so as to control a current that is supplied to charge the capacitor.

Abstract translation: 集成电路包括电容器。 开关以并联方式与电容器电耦合。 比较器包括第一输入节点，第二输入节点和输出节点。 第二输入节点与电容器的第一板电耦合。 输出节点与开关电耦合。 晶体管与电容器的第二板电耦合。 电路与晶体管的栅极电耦合。 电路被配置为向晶体管的栅极提供偏置电压，以便控制供给电容器充电的电流。

公开(公告)号：US08350339B2

公开(公告)日：2013-01-08

申请号：US12795144

申请日：2010-06-07

Applicant: Mei-Hui Huang ,  Chan-Hong Chern

Inventor： Mei-Hui Huang ,  Chan-Hong Chern

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L27/088 ,  H01L21/823425 ,  H01L21/823437 ,  H01L27/0207 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/42372 ,  H01L29/66545

Abstract: An integrated circuit includes at least one first gate electrode of at least one active transistor. At least one first dummy gate electrode is disposed adjacent to a first side edge of the at least one first gate electrode. At least one second dummy gate electrode is disposed adjacent to a second side edge of the at least one first gate electrode. The second side edge is opposite to the first side edge. At least one guard ring is disposed around the at least one first gate electrode, the at least one first dummy gate electrode, and the at least one second dummy gate electrode. An ion implantation layer of the at least one guard ring substantially touches at least one of the at least one first dummy gate electrode and the at least one second dummy gate electrode.

Abstract translation: 集成电路包括至少一个有源晶体管的第一栅电极。 至少一个第一虚拟栅电极设置成与所述至少一个第一栅电极的第一侧边缘相邻。 至少一个第二伪栅电极设置成与所述至少一个第一栅电极的第二侧边相邻。 第二侧边缘与第一侧边缘相对。 至少一个保护环布置在所述至少一个第一栅电极，所述至少一个第一虚拟栅极电极和所述至少一个第二虚拟栅电极周围。 所述至少一个保护环的离子注入层基本上接触所述至少一个第一伪栅极电极和所述至少一个第二虚设栅极电极中的至少一个。

公开(公告)号：US20120217586A1

公开(公告)日：2012-08-30

申请号：US13035533

申请日：2011-02-25

Applicant: Chan-Hong CHERN ,  Fu-Lung HSUEH

Inventor： Chan-Hong CHERN ,  Fu-Lung HSUEH

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L27/1207 ,  H01L28/20 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4975

Abstract: A method of forming an integrated circuit includes forming at least one transistor over a substrate. The at least one transistor includes a first gate dielectric structure disposed over a substrate. A work-function metallic layer is disposed over the first gate dielectric structure. A conductive layer is disposed over the work-function metallic layer. A source/drain (S/D) region is disposed adjacent to each sidewall of the first gate dielectric structure. At least one resistor structure is formed over the substrate. The at least one resistor structure includes a first doped semiconductor layer disposed over the substrate. The at least one resistor structure does not include any work-function metallic layer between the first doped semiconductor layer and the substrate.

Abstract translation: 形成集成电路的方法包括在衬底上形成至少一个晶体管。 所述至少一个晶体管包括设置在衬底上的第一栅极电介质结构。 工作功能金属层设置在第一栅极电介质结构上。 导电层设置在功函数金属层上。 源极/漏极（S / D）区域邻近第一栅极电介质结构的每个侧壁设置。 在衬底上形成至少一个电阻器结构。 所述至少一个电阻器结构包括设置在所述衬底上的第一掺杂半导体层。 至少一个电阻器结构不包括在第一掺杂半导体层和衬底之间的任何功函数金属层。

公开(公告)号：US20120161742A1

公开(公告)日：2012-06-28

申请号：US12976504

申请日：2010-12-22

Applicant: Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Chih-Chang LIN

Inventor： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Chih-Chang LIN

IPC: G05F5/08

CPC classification number: G05F1/648 ,  G11C5/147 ,  H02M3/158

Abstract: A current generator includes an op-amp having a negative terminal arranged to be coupled to an input voltage, a resistance selection circuit having at least one tunable resistor connected with each other, and at least one power transistor. A gate of the at least one power transistor is coupled to an output of the op-amp, and a drain of the at least one power transistor is coupled to the at least one tunable resistor or a load. The resistance selection circuit is configured to select a node of the at least one tunable resistor based on the input voltage for coupling from a positive terminal of the op-amp. The at least one tunable resistor is configured to adjust a resistance setting to control a current level of the current generator based on a power supply voltage or a current of a reference resistor.

Abstract translation: 电流发生器包括具有布置为耦合到输入电压的负极端子的运算放大器，具有彼此连接的至少一个可调电阻器的电阻选择电路和至少一个功率晶体管。 所述至少一个功率晶体管的栅极耦合到所述运算放大器的输出，并且所述至少一个功率晶体管的漏极耦合到所述至少一个可调电阻器或负载。 电阻选择电路被配置为基于用于从运算放大器的正极端子耦合的输入电压来选择至少一个可调电阻器的节点。 所述至少一个可调电阻器被配置为基于电源电压或参考电阻器的电流来调整电阻设置以控制电流发生器的电流水平。

公开(公告)号：US08207775B2

公开(公告)日：2012-06-26

申请号：US12871343

申请日：2010-08-30

Applicant: Chan-Hong Chern ,  Fu-Lung Hsueh ,  Yuwen Swei ,  Chih-Chang Lin

Inventor： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Yuwen Swei ,  Chih-Chang Lin

IPC: H03L5/00

CPC classification number: H03K19/0941 ,  H03K3/356182 ,  H03K19/018514

Abstract: A representative level-shifter comprises a dynamically biased current source circuit that receives a first voltage, a first and a second unidirectional current-conducting devices, a first and a second pull-down devices, and a pull-up device. The first and second unidirectional current-conducting devices are coupled to the dynamically biased current source circuit. A voltage output of the level-shifter is located at a first node that is located between the current-constant circuit and the second unidirectional current-conducting device. The first and second pull-down devices are coupled to the first and second unidirectional current-conducting devices, respectively. The pull-up device receives a second voltage and is coupled to the dynamically biased current source circuit and the first unidirectional current-conducting device. The pull-up device is configured to dynamically bias the dynamically biased current source circuit such that a voltage drop of the second unidirectional current-conducting device is output at the voltage output responsive to the pull-up device outputting the second voltage to the dynamically biased current source circuit, the first pull-down device being non-conducting and the second pull-down device being conducting.

Abstract translation: 代表性的电平转换器包括接收第一电压，第一和第二单向导流器件，第一和第二下拉器件以及上拉器件的动态偏置电流源电路。 第一和第二单向导流器件耦合到动态偏置电流源电路。 电平移位器的电压输出位于位于电流恒定电路和第二单向导流器件之间的第一节点处。 第一和第二下拉装置分别耦合到第一和第二单向导流装置。 上拉装置接收第二电压并耦合到动态偏置电流源电路和第一单向导流装置。 上拉装置被配置为动态地偏置动态偏置的电流源电路，使得第二单向导流装置的电压降在电压输出处被输出，响应于上拉装置将第二电压输出到动态偏置 电流源电路，第一下拉装置不导通，第二下拉装置导通。

公开(公告)号：US08183913B2

公开(公告)日：2012-05-22

申请号：US12706886

申请日：2010-02-17

Applicant: Steven Swei ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Chan-Hong Chern ,  Ming-Chieh Huang

Inventor： Steven Swei ,  Chih-Chang Lin ,  Tien-Chun Yang ,  Chan-Hong Chern ,  Ming-Chieh Huang

IPC: G05F1/10 ,  G05F3/02

CPC classification number: G05F1/10 ,  G05F3/02 ,  H03L7/0895 ,  H03L7/0896 ,  H03L7/0898

Abstract: An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.

Abstract translation: 集成电路包括第一电流源。 第二电流源经由导线与第一电流源电耦合。 开关电路耦合在第一电流源和第二电流源之间。 第一电路耦合在第一节点和第二节点之间。 第一节点设置在第一电流源和开关电路之间。 第二节点与第一电流源耦合。 第一电路被配置为基本上均衡第一节点和第二节点上的电压。 第二电路耦合在第三节点和第四节点之间。 第三节点设置在第二电流源和开关电路之间。 第四节点被布置成与第二电流源耦合。 第二电路被配置为基本上均衡第三节点和第四节点上的电压。

公开(公告)号：US20120050930A1

公开(公告)日：2012-03-01

申请号：US12871343

申请日：2010-08-30

Applicant: Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Yuwen SWEI ,  Chih-Chang LIN

Inventor： Chan-Hong CHERN ,  Fu-Lung HSUEH ,  Yuwen SWEI ,  Chih-Chang LIN

IPC: H02H9/04 ,  H03L5/00

CPC classification number: H03K19/0941 ,  H03K3/356182 ,  H03K19/018514

Abstract: A representative level-shifter comprises a dynamically biased current source circuit that receives a first voltage, a first and a second unidirectional current-conducting devices, a first and a second pull-down devices, and a pull-up device. The first and second unidirectional current-conducting devices are coupled to the dynamically biased current source circuit. A voltage output of the level-shifter is located at a first node that is located between the current-constant circuit and the second unidirectional current-conducting device. The first and second pull-down devices are coupled to the first and second unidirectional current-conducting devices, respectively. The pull-up device receives a second voltage and is coupled to the dynamically biased current source circuit and the first unidirectional current-conducting device. The pull-up device is configured to dynamically bias the dynamically biased current source circuit such that a voltage drop of the second unidirectional current-conducting device is output at the voltage output responsive to the pull-up device outputting the second voltage to the dynamically biased current source circuit, the first pull-down device being non-conducting and the second pull-down device being conducting.

Abstract translation: 代表性的电平转换器包括接收第一电压，第一和第二单向导流器件，第一和第二下拉器件以及上拉器件的动态偏置电流源电路。 第一和第二单向导流器件耦合到动态偏置电流源电路。 电平移位器的电压输出位于位于电流恒定电路和第二单向导流器件之间的第一节点处。 第一和第二下拉装置分别耦合到第一和第二单向导流装置。 上拉装置接收第二电压并耦合到动态偏置电流源电路和第一单向导流装置。 上拉装置被配置为动态地偏置动态偏置的电流源电路，使得第二单向导流装置的电压降在电压输出处被输出，响应于上拉装置将第二电压输出到动态偏置 电流源电路，第一下拉装置不导通，第二下拉装置导通。