公开(公告)号：US08549212B2

公开(公告)日：2013-10-01

申请号：US12641612

申请日：2009-12-18

Applicant: Chao-Hsin Lu

Inventor： Chao-Hsin Lu

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7202

Abstract: The invention provides a flash storage device. In one embodiment, the flash storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks, wherein each of the plurality of blocks comprises a plurality of pages for storing data, and each of the plurality of pages has a physical address. The controller divides a plurality of logical addresses into a plurality of logical address ranges, records a plurality of partial link tables respectively storing a mapping relationship between logical addresses of a corresponding logical address range and corresponding physical addresses, stores the partial link tables in the flash memory, combines the partial link tables to obtain a link table, and converts logical addresses sent by a host to physical addresses according to the link table.

Abstract translation: 本发明提供一种闪存存储装置。 在一个实施例中，闪存存储设备包括闪存和控制器。 闪速存储器包括多个块，其中多个块中的每个块包括用于存储数据的多个页面，并且多个页面中的每一个具有物理地址。 控制器将多个逻辑地址划分为多个逻辑地址范围，记录分别存储对应的逻辑地址范围的逻辑地址与对应的物理地址之间的映射关系的多个部分链接表，将部分链接表存储在闪存中 存储器，组合部分链接表以获得链接表，并且根据链接表将主机发送的逻辑地址转换为物理地址。

公开(公告)号：US07995979B2

公开(公告)日：2011-08-09

申请号：US12041664

申请日：2008-03-04

Applicant: Chao-Hsin Lu ,  Chang-Fu Kuo

Inventor： Chao-Hsin Lu ,  Chang-Fu Kuo

IPC: H04B17/02 ,  H04B7/00

CPC classification number: G01S19/23 ,  H03G3/3052

Abstract: A wireless receiver with automatic gain control and a method for automatic gain control of a receiving circuit utilized in a wireless receiver are provided. The receiving circuit includes a programmable gain amplifier and a low noise amplifier, and the method includes: comparing a gain code of the programmable gain amplifier with a predetermined code range, wherein the gain code is determined by a frequency signal received through the low noise amplifier; and adjusting a gain of the low noise amplifier when the gain code is out of the predetermined code range.

Abstract translation: 提供一种具有自动增益控制的无线接收机和用于无线接收机中的接收电路的自动增益控制方法。 接收电路包括可编程增益放大器和低噪声放大器，该方法包括：将可编程增益放大器的增益代码与预定代码范围进行比较，其中增益代码由通过低噪声放大器接收的频率信号确定 ; 以及当所述增益代码超出所述预定代码范围时调整所述低噪声放大器的增益。

公开(公告)号：US07372298B2

公开(公告)日：2008-05-13

申请号：US11277361

申请日：2006-03-24

Applicant: Hung-Jen Chu ,  Chao-Hsin Lu ,  Shiu-Rong Tong ,  Yu-Pin Chou

Inventor： Hung-Jen Chu ,  Chao-Hsin Lu ,  Shiu-Rong Tong ,  Yu-Pin Chou

IPC: H03K19/173 ,  H03K19/00

CPC classification number: G06F1/22 ,  H03K19/1732

Abstract: A chip with an adjustable pinout function is disclosed. The chip includes a first pinout, a second pinout, a logic circuit, and a selecting circuit. The logic circuit includes a first port and a second port. The selecting circuit, which is coupled to the logic circuit, the first pinout, and the second pinout, controls the first pinout to be coupled to the first port or the second port, and controls the second pinout to be coupled to the first port or the second port.

Abstract translation: 公开了一种具有可调节引脚排列功能的芯片。 芯片包括第一引脚，第二引脚，逻辑电路和选择电路。 逻辑电路包括第一端口和第二端口。 耦合到逻辑电路，第一引脚排列和第二引脚分布的选择电路控制第一引脚被耦合到第一端口或第二端口，并且控制第二引脚分布以耦合到第一端口或 第二个港口。

公开(公告)号：US20080030584A1

公开(公告)日：2008-02-07

申请号：US11878564

申请日：2007-07-25

Applicant: Jui-Yuan Tsai ,  Chao-Hsin Lu

Inventor： Jui-Yuan Tsai ,  Chao-Hsin Lu

IPC: H04N5/225 ,  H03M1/12 ,  H04N5/455

CPC classification number: H04N5/0675

Abstract: The invention discloses an image processing system comprising a video source system, a transmission medium, and a television system. The image processing systems of the video source system and the television system are equipped with an additional digital-to-analog converter and an additional analog-to-digital converter.

Abstract translation: 本发明公开了一种包括视频源系统，传输介质和电视系统的图像处理系统。 视频源系统和电视系统的图像处理系统配备有附加的数模转换器和附加的模拟 - 数字转换器。

公开(公告)号：US20080025453A1

公开(公告)日：2008-01-31

申请号：US11865874

申请日：2007-10-02

Applicant: Chao-Hsin Lu

Inventor： Chao-Hsin Lu

IPC: H03D3/24

CPC classification number: H03L7/093 ,  H03L7/0812 ,  H04L7/0331

Abstract: A sampling-error phase compensating device and a method thereof for sequentially sampling data signals and outputting sampled data signals. The method sequentially includes the steps of: sampling each data signal according to a first sampling clock signal, and sequentially outputting corresponding phase detection signals according to the sampled data signals; sequentially outputting phase regulating signals, which correspond to the phase detection signals, respectively, according to the phase detection signals, wherein when the phase detection signals are the same, the phase regulating signals includes first-state phase regulating signals and second-state phase regulating signals, the first-state phase regulating signals correspond to the phase detection signals, and the number of the second-state phase regulating signals is smaller than that of the first-state phase regulating signals; and sequentially outputting second sampling clock signals according to the phase regulating signals, wherein phases of the sampling clock signals correspond to those of the phase regulating signals, respectively.

Abstract translation: 一种采样误差相位补偿装置及其方法，用于顺序采样数据信号并输出​​采样数据信号。 该方法顺序地包括以下步骤：根据第一采样时钟信号对每个数据信号进行采样，并根据采样数据信号依次输出相应的相位检测信号; 根据相位检测信号分别顺序地输出与相位检测信号相对应的相位调制信号，其中当相位检测信号相同时，相位调节信号包括第一状态相位调节信号和第二状态相位调节 信号，第一状态相位调节信号对应于相位检测信号，并且第二状态相位调节信号的数量小于第一状态相位调制信号的数量; 并且根据相位调节信号依次输出第二采样时钟信号，其中采样时钟信号的相位分别对应于相位调制信号的相位。

公开(公告)号：US07279944B2

公开(公告)日：2007-10-09

申请号：US11268505

申请日：2005-11-08

Applicant: Chao-Hsin Lu

Inventor： Chao-Hsin Lu

IPC: H03L7/00

CPC classification number: G06F1/10 ,  G06F1/06

Abstract: A clock signal generator and method thereof are provided for a system to generate an output signal. The apparatus comprises: a delay circuit for generating a delayed clock with a first time, a delay module for generating delayed signal(s), and a decision circuit for comparing the delayed signal(s) with the delayed clock to obtain the relative relation between the delay time and the first time and controlling a delay time of an input signal according to the relative relation to generate the output signal.

Abstract translation: 提供了一种用于系统产生输出信号的时钟信号发生器及其方法。 该装置包括：用于产生第一时间的延迟时钟的延迟电路，用于产生延迟信号的延迟模块，以及用于将延迟的信号与延迟时钟进行比较的判定电路，以获得延迟时间之间的相对关系 延迟时间和第一时间，并且根据相对关系控制输入信号的延迟时间以产生输出信号。

公开(公告)号：US20070071157A1

公开(公告)日：2007-03-29

申请号：US11469878

申请日：2006-09-04

Applicant: Chao-Hsin Lu

Inventor： Chao-Hsin Lu

IPC: H03D3/24

CPC classification number: H03L7/0893 ,  H04L7/033

Abstract: A clock recovery circuit for generating an output clock corresponding to an input signal is disclosed. The clock recovery circuit includes: a phase detection unit for receiving the input signal and the output clock and generating a phase error signal according to the input signal and the output clock; a serial-to-parallel converting unit coupled to the phase detection unit for converting the serial phase error signal to a plurality of parallel phase error signals; a plurality of charging/discharging units coupled to the serial-to-parallel converting unit for generating an adjustment signal according to the parallel phase error signals; and an oscillator for generating the output clock according to the adjustment signal.

Abstract translation: 公开了一种用于产生与输入信号对应的输出时钟的时钟恢复电路。 时钟恢复电路包括：相位检测单元，用于接收输入信号和输出时钟，并根据输入信号和输出时钟产生相位误差信号; 串联到并行转换单元，耦合到相位检测单元，用于将串行相位误差信号转换成多个并行相位误差信号; 耦合到所述串并转换单元的多个充电/放电单元，用于根据并行相位误差信号产生调整信号; 以及用于根据调整信号产生输出时钟的振荡器。

公开(公告)号：US20060097767A1

公开(公告)日：2006-05-11

申请号：US11268505

申请日：2005-11-08

Applicant: Chao-Hsin Lu

Inventor： Chao-Hsin Lu

IPC: G06F1/04

CPC classification number: G06F1/10 ,  G06F1/06

Abstract: A clock signal generator and method thereof are provided for a system to generate an output signal. The apparatus comprises: a delay circuit for generating a delayed clock with a first time, a delay module for generating delayed signal(s), and a decision circuit for comparing the delayed signal(s) with the delayed clock to obtain the relative relation between the delay time and the first time and controlling a delay time of an input signal according to the relative relation to generate the output signal.

Abstract translation: 提供了一种用于系统产生输出信号的时钟信号发生器及其方法。 该装置包括：用于产生第一时间的延迟时钟的延迟电路，用于产生延迟信号的延迟模块，以及用于将延迟的信号与延迟时钟进行比较的判定电路，以获得延迟时间之间的相对关系 延迟时间和第一时间，并且根据相对关系控制输入信号的延迟时间以产生输出信号。

公开(公告)号：US20060023380A1

公开(公告)日：2006-02-02

申请号：US11193365

申请日：2005-08-01

Applicant: Chao-Hsin Lu

Inventor： Chao-Hsin Lu

IPC: H02H9/00

CPC classification number: H02H9/046

Abstract: An ESD (Electrostatic Discharge) circuit used in a multi-voltage system for protecting the system from electrostatic discharge between a first voltage source and at least one second voltage source. The ESD circuit includes a voltage bus, a first ESD protection circuit coupled between the first voltage source and the voltage bus, and a second ESD protection circuit coupled between the voltage bus and the second voltage source. The first ESD protection circuit includes an ESD detecting unit for detecting an electrostatic voltage and generating a trigger signal, and an ESD discharge unit for receiving the trigger signal of the ESD detecting unit and discharging an electrostatic current according to the trigger signal.

Abstract translation: 一种用于多电压系统中的ESD（静电放电）电路，用于保护系统免受第一电压源和至少一个第二电压源之间的静电放电。 ESD电路包括电压总线，耦合在第一电压源和电压总线之间的第一ESD保护电路，以及耦合在电压总线和第二电压源之间的第二ESD保护电路。 第一ESD保护电路包括用于检测静电电压并产生触发信号的ESD检测单元，以及用于接收ESD检测单元的触发信号并根据触发信号放电静电电流的ESD放电单元。

公开(公告)号：US20050156678A1

公开(公告)日：2005-07-21

申请号：US10930234

申请日：2004-08-31

Applicant: Chao-Hsin Lu

Inventor： Chao-Hsin Lu

IPC: H03K3/012 ,  H03K3/03 ,  H03L7/099 ,  H03B1/00

CPC classification number: H03K3/012 ,  H03K3/0322 ,  H03L7/0995

Abstract: A voltage control oscillator includes a regulator and several voltage controlled delay cells. The regulator receives a control voltage and outputs an operation voltage. The voltage controlled delay cells are coupled to each other in serial to form a feedback circuit for outputting a clock signal. The delay cell includes a first inverter, a second inverter, and a cross latch. The first inverter receives a first input signal and outputs a first output signal, and the second inverter receives a second input signal and outputs a second output signal. The cross latch is used for latching the first output signal and the second output signal.

Abstract translation: 电压控制振荡器包括调节器和若干电压控制延迟单元。 调节器接收控制电压并输出工作电压。 电压控制延迟单元串联耦合以形成用于输出时钟信号的反馈电路。 延迟单元包括第一反相器，第二反相器和交叉锁存器。 第一反相器接收第一输入信号并输出​​第一输出信号，第二反相器接收第二输入信号并输出​​第二输出信号。 交叉锁存器用于锁存第一输出信号和第二输出信号。