公开(公告)号：US07932748B1

公开(公告)日：2011-04-26

申请号：US12640724

申请日：2009-12-17

Applicant: Ming-Dou Ker ,  Yan-Liang Lin ,  Chua-Chin Wang

Inventor： Ming-Dou Ker ,  Yan-Liang Lin ,  Chua-Chin Wang

IPC: H03K19/0175

CPC classification number: H03K19/018592 ,  H03K19/00384 ,  H03K19/018507

Abstract: A 2×VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature (PVT) compensation suitable for CMOS technology is disclosed. A 2×VDD-tolerant I/O buffer with a PVT compensation circuit is implemented with novel 2×VDD-tolerant logic gates. Output slew rate variations can be kept within smaller ranges to match maximum and minimum timing specifications. A 2×VDD tolerant logic circuit for implementing the I/O buffer is also disclosed.

公开(公告)号：US20110026175A1

公开(公告)日：2011-02-03

申请号：US12562426

申请日：2009-09-18

Applicant: Ming-Dou Ker ,  Chang-Tzu Wang ,  Chua-Chin Wang

Inventor： Ming-Dou Ker ,  Chang-Tzu Wang ,  Chua-Chin Wang

IPC: H02H9/04

CPC classification number: H01L27/0262 ,  H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to an electrostatic discharge protecting circuit with ultra-low standby leakage current for twice supply voltage tolerance. The electrostatic discharge protecting circuit of the invention includes a substrate driver, a third transistor, a start-up circuit, a RC circuit and a second resistor. The substrate driver has a first transistor and a second transistor in serious connection. The start-up circuit has a fourth transistor and a fifth transistor with diode-connected. The RC circuit has a first resistor, a sixth transistor and a seventh transistor in serious connection. Compared with the prior art, the electrostatic discharge protecting circuit with ultra-low standby leakage current for twice supply voltage tolerance of the invention with advantages of low standby leakage current, high ESD robustness, and no gate-oxide reliability issue is an excellent circuit solution for on-chip ESD protection design for mixed-voltage I/O buffers in nanometer CMOS technologies.

Abstract translation: 本发明涉及具有超低电源电压容限的超低待机漏电流的静电放电保护电路。 本发明的静电放电保护电路包括衬底驱动器，第三晶体管，启动电路，RC电路和第二电阻器。 衬底驱动器具有严格连接的第一晶体管和第二晶体管。 启动电路具有第四晶体管和具有二极管连接的第五晶体管。 RC电路具有严重连接的第一电阻器，第六晶体管和第七晶体管。 与现有技术相比，具有超低待机漏电电流的静电放电保护电路具有本发明两倍的电源电压公差，具有低待机漏电流，高ESD稳健性和无栅极氧化可靠性问题的优点，是一种极好的电路解决方案 用于纳米CMOS技术的混合电压I / O缓冲器的片上ESD保护设计。

公开(公告)号：US20060227594A1

公开(公告)日：2006-10-12

申请号：US11093766

申请日：2005-03-30

Applicant: Chua-Chin Wang ,  Tien-Hao Chen

Inventor： Chua-Chin Wang ,  Tien-Hao Chen

IPC: G11C11/00

CPC classification number: G11C11/413 ,  G11C8/08

Abstract: The invention relates to an integrated circuit memory unit comprising: a memory cell, a switched bulk DC voltage source and a plurality of wordline-controlled transistors. Each of wordline-controlled transistors has a bulk connected to the switched bulk DC voltage source. When the data bit is read from the memory cell or the data bit is written into the memory cell, the bulks of the wordline-controlled transistors are switched to a first voltage level from the switched bulk DC voltage source so as to increase the drain current and obtain faster operation speed. When in an idle mode, the bulks of the wordline-controlled transistors are switched to a second voltage level from the switched bulk DC voltage source so as to obtain higher threshold voltage and decrease the leakage current.

Abstract translation: 本发明涉及一种集成电路存储单元，包括：存储单元，开关体积直流电压源和多个字线控制晶体管。 字线控制晶体管中的每一个具有大量连接到开关体积直流电压源。 当从存储器单元读取数据位或将数据位写入存储单元时，将字线控制的晶体管的体积从切换体积直流电压源切换到第一电压电平，从而增加漏极电流 并获得更快的运行速度。 当处于空闲模式时，字线控制晶体管的体积从切换的体积直流电压源切换到第二电压电平，从而获得更高的阈值电压并减小漏电流。

公开(公告)号：US20060146972A1

公开(公告)日：2006-07-06

申请号：US11179847

申请日：2005-07-12

Applicant: Chua-Chin Wang ,  Ming-Kai Chang ,  Ling-Shiou Huang

Inventor： Chua-Chin Wang ,  Ming-Kai Chang ,  Ling-Shiou Huang

IPC: H03D3/24

CPC classification number: H03L7/085

Abstract: A method and a circuit for resolving the out-of-phase problem between a color burst signal and a sub-carrier signal of a television system. A delay means is used which leads to the synchronization of the color burst signal and the sub-carrier signal such that a subsequent color demodulator can demodulate correct color signals. Therefore, the locking of the two signals will be fastened without any excessively large circuit hardware.

公开(公告)号：US20130218473A1

公开(公告)日：2013-08-22

申请号：US13592010

申请日：2012-08-22

Applicant: Chua-Chin Wang ,  Chia-Hao Hsu ,  I-Yu Huang ,  Yun-Chi Chen ,  Yue-Da Tsai ,  Ming-Chih Lee

Inventor： Chua-Chin Wang ,  Chia-Hao Hsu ,  I-Yu Huang ,  Yun-Chi Chen ,  Yue-Da Tsai ,  Ming-Chih Lee

IPC: G06F19/00

CPC classification number: G01N33/6848

Abstract: A frequency shift detector includes a digital control unit, a digital/analog converter, a reagent concentration detecting circuit and a frequency difference generator, wherein the digital control unit includes a control circuit and a direct digital frequency synthesizer electrically connected with the control circuit, and the control circuit comprises a reset terminal and a pulse input terminal. The digital control unit proceeds with accurate concentration detection for various samples borne on the reagent concentration detecting circuit.

Abstract translation: 一种频移检测器，包括数字控制单元，数字/模拟转换器，试剂浓度检测电路和频差发生器，其中数字控制单元包括与控制电路电连接的控制电路和直接数字频率合成器，以及 控制电路包括复位端和脉冲输入端。 数字控制单元对于试剂浓度检测电路上承载的各种样品进行准确的浓度检测。

公开(公告)号：US08219190B2

公开(公告)日：2012-07-10

申请号：US12581915

申请日：2009-10-20

Applicant: Chua-Chin Wang ,  Tzung-Je Lee

Inventor： Chua-Chin Wang ,  Tzung-Je Lee

IPC: A61N1/00

CPC classification number: A61N1/32 ,  A61N1/36071 ,  A61N1/3787

Abstract: The invention relates to an implantable biomedical chip with modulator for a wireless neural stimulating system. The implantable biomedical chip comprises a power regulator, a demodulator, a baseband circuit, a D/A converter, an instrumentation amplifier, an A/D converter and a modulator. According to the invention, the modulator is mounted on the implantable biomedical chip, and can achieve full-duplex communication to improve the controllability and observability. Besides, the power consumption and area occupation is reduced as compared with using discrete components. Therefore, the integration of the implantable biomedical chip can be easily accomplished.

Abstract translation: 本发明涉及一种具有用于无线神经刺激系统的调制器的可植入生物医学芯片。 可植入生物医学芯片包括功率调节器，解调器，基带电路，D / A转换器，仪表放大器，A / D转换器和调制器。 根据本发明，调制器安装在可植入的生物医学芯片上，并且可以实现全双工通信以提高可控性和可观察性。 此外，与使用分立元件相比，功耗和占地面积减少。 因此，可以容易地实现植入式生物医学芯片的集成。

公开(公告)号：US20110241752A1

公开(公告)日：2011-10-06

申请号：US13067598

申请日：2011-06-13

Applicant: Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

Inventor： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

IPC: H03K5/08

CPC classification number: H03K19/0013 ,  H03K3/356113 ,  H03K19/018521

Abstract: A mixed-voltage I/O buffer includes an input buffer circuit. The input buffer circuit includes a first inverter, a first voltage level limiting circuit, a first voltage level pull-up circuit, an input stage circuit, and a logic calibration circuit. The first inverter inverts an input signal to generate a first control signal. The first voltage level limiting circuit limits voltage level of an external signal to generate the input signal transmitted to the first inverter to prevent electrical overstress of the first inverter. The first voltage level pull-up circuit is controlled by the first control signal to pull up voltage level of the input signal inputted into the first inverter. The input stage circuit receives the first control signal to generate corresponding digital signals inputted into a core circuit. The logic calibration circuit calibrates voltage level of the first control signal when the first inverter mis-operates due to the input signal having a low voltage level.

Abstract translation: 混合电压I / O缓冲器包括输入缓冲电路。 输入缓冲电路包括第一反相器，第一电压电平限制电路，第一电压电平上拉电路，输入级电路和逻辑校准电路。 第一反相器反相输入信号以产生第一控制信号。 第一电压电平限制电路限制外部信号的电压电平，以产生传输到第一逆变器的输入信号，以防止第一逆变器的电过载。 第一电压上拉电路由第一控制信号控制，以提高输入到第一反相器的输入信号的电压电平。 输入级电路接收第一控制信号以产生输入到核心电路的相应的数字信号。 当由于输入信号具有低电压电平而使第一反相器误操作时，逻辑校准电路校准第一控制信号的电压电平。

公开(公告)号：US20110127971A1

公开(公告)日：2011-06-02

申请号：US12727263

申请日：2010-03-19

Applicant: CHUA-CHIN WANG ,  SHAO-FU YEN ,  JR-SHANG SHIE

Inventor： CHUA-CHIN WANG ,  SHAO-FU YEN ,  JR-SHANG SHIE

IPC: H02J7/06 ,  H02J7/04

CPC classification number: H02J7/0086

Abstract: A charging circuit integrated into a chip, comprising a charging unit, a switch unit, a biasing unit, a voltage-dividing unit, and a comparing unit. The charging unit is connected between a power supply input and a load for outputting a constant current based on a constant bias voltage supplied by the power supply input in order to charge the load. The switch unit is connected between the charging unit and the power supply input for turning on or cutting off the charging unit. The voltage-dividing unit generates a first signal to the comparing unit according to a voltage of the load. The biasing unit outputs a second signal having a constant voltage to the comparing unit. The comparing unit compares the first signal with the second signal for cutting off or turning on the switch unit, bringing the charging unit to charge or stop charging the load, respectively.

Abstract translation: 集成在芯片中的充电电路，包括充电单元，开关单元，偏压单元，分压单元和比较单元。 充电单元连接在电源输入和用于输出恒定电流的负载之间，基于由电源输入提供的恒定偏置电压以对负载充电。 开关单元连接在充电单元和电源输入端之间，用于打开或切断充电单元。 分压单元根据负载的电压向比较单元产生第一信号。 偏置单元向比较单元输出具有恒定电压的第二信号。 比较单元将第一信号与用于切断或接通开关单元的第二信号进行比较，使充电单元分别对负载充电或停止充电。

公开(公告)号：US07839174B2

公开(公告)日：2010-11-23

申请号：US12330768

申请日：2008-12-09

Applicant: Chua-Chin Wang ,  Tzung-Je Lee ,  Yi-Cheng Liu ,  Kuo-Chan Huang

Inventor： Chua-Chin Wang ,  Tzung-Je Lee ,  Yi-Cheng Liu ,  Kuo-Chan Huang

IPC: H03K19/094

CPC classification number: H03K19/018521

Abstract: An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein.

Abstract translation: 输出缓冲电路包括高电压检测电路，动态栅极偏置产生电路，输出级电路和焊盘电压检测器。 高电压检测电路检测电源电压，并根据电源电压产生第一和第二确定信号以及第一和第二偏置电压。 动态栅极偏置产生电路被第一和第二偏置电压偏置，并接收第一和第二确定信号，用于根据第一和第二确定信号将逻辑控制信号转换成相应的栅极偏置电压。 焊盘电压检测器检测I / O焊盘的电压，并为输出级电路提供焊盘电压检测信号，以修改输出到I / O焊盘的输出信号。 本文公开了混合电压输入/输出（I / O）缓冲器。

公开(公告)号：US20100168828A1

公开(公告)日：2010-07-01

申请号：US12581915

申请日：2009-10-20

Applicant: Chua-Chin Wang ,  Tzung-Je Lee

Inventor： Chua-Chin Wang ,  Tzung-Je Lee

IPC: A61N1/36

CPC classification number: A61N1/32 ,  A61N1/36071 ,  A61N1/3787

Abstract: The invention relates to an implantable biomedical chip with modulator for a wireless neural stimulating system. The implantable biomedical chip comprises a power regulator, a demodulator, a baseband circuit, a D/A converter, an instrumentation amplifier, an A/D converter and a modulator. According to the invention, the modulator is mounted on the implantable biomedical chip, and can achieve full-duplex communication to improve the controllability and observability. Besides, the power consumption and area occupation is reduced as compared with using discrete components. Therefore, the integration of the implantable biomedical chip can be easily accomplished.

Abstract translation: 本发明涉及一种具有用于无线神经刺激系统的调制器的可植入生物医学芯片。 可植入生物医学芯片包括功率调节器，解调器，基带电路，D / A转换器，仪表放大器，A / D转换器和调制器。 根据本发明，调制器安装在可植入的生物医学芯片上，并且可以实现全双工通信以提高可控性和可观察性。 此外，与使用分立元件相比，功耗和占地面积减少。 因此，可以容易地实现植入式生物医学芯片的集成。