公开(公告)号：US07877647B2

公开(公告)日：2011-01-25

申请号：US10444451

申请日：2003-05-23

Applicant: Dwight D. Riley

Inventor： Dwight D. Riley

IPC: G06F11/00

CPC classification number: G06F11/10

Abstract: As disclosed herein, an interface for a device adapted to couple to an interconnect may comprise decode and error check logic and a plurality of decode logic units. The decode and error check logic may receive error check bits and a target address from the interconnect and may determine whether the target address was received in error. At least one of the decode logic units also may receive the error check bits and correct the target address using the error check bits in parallel with the decode and error check logic determining whether the target address was received in error.

Abstract translation: 如本文所公开的，适于耦合到互连的设备的接口可以包括解码和错误校验逻辑以及多个解码逻辑单元。 解码和错误检查逻辑可以从互连接收错误校验位和目标地址，并且可以确定目标地址是否被错误地接收。 解码逻辑单元中的至少一个还可以使用与解码和错误校验逻辑并行的错误校验位来接收错误校验位并校正目标地址，以确定目标地址是否被错误地接收。

公开(公告)号：US20090113430A1

公开(公告)日：2009-04-30

申请号：US11930854

申请日：2007-10-31

Applicant: Dwight D. RILEY

Inventor： Dwight D. RILEY

IPC: G06F9/46 ,  G06F13/36 ,  G06F13/00

CPC classification number: G06F9/468 ,  G06F21/44 ,  G06F21/53 ,  G06F21/606

Abstract: A hardware device interface supporting transaction authentication is described herein. At least some illustrative embodiments include a device, including an interconnect interface, and processing logic (coupled to the bus interface) that provides access to a plurality of functions of the device through the interconnect interface. A first transaction received by the device, and associated with a function of the plurality of functions, causes a request identifier within the first transaction to be assigned to the function. Access to the function is denied if a request identifier of a second transaction, subsequent to the first transaction, does not match the request identifier assigned to the function.

Abstract translation: 本文描述了支持事务认证的硬件设备接口。 至少一些说明性实施例包括通过互连接口提供对设备的多个功能的访问的设备，包括互连接口和处理逻辑（耦合到总线接口）。 由设备接收并与多个功能的功能相关联的第一事务使第一事务中的请求标识符被分配给该功能。 如果在第一个事务之后的第二个事务的请求标识符与分配给该函数的请求标识符不匹配，则对该函数的访问被拒绝。

公开(公告)号：US20090070775A1

公开(公告)日：2009-03-12

申请号：US11851306

申请日：2007-09-06

Applicant: Dwight D. Riley

Inventor： Dwight D. Riley

IPC: G06F9/54

CPC classification number: H04L49/35 ,  H04L49/65

Abstract: Systems and methods of sharing legacy devices in a multi-host environment are disclosed. An exemplary method for sharing legacy devices in a multi-host environment includes receiving device information from a legacy device, the device information identifying a target within a virtual machine. The method also includes encapsulating the device information into a corresponding bus transaction for a network switch fabric. The method also includes routing the bus transaction over the network switch fabric in the virtual machine to a host within the virtual machine.

Abstract translation: 公开了在多主机环境中共享传统设备的系统和方法。 用于在多主机环境中共享传统设备的示例性方法包括从传统设备接收设备信息，所述设备信息标识虚拟机内的目标。 该方法还包括将设备信息封装成用于网络交换结构的相应总线事务。 该方法还包括将虚拟机中的网络交换机结构上的总线事务路由到虚拟机内的主机。

公开(公告)号：US20090016348A1

公开(公告)日：2009-01-15

申请号：US11775967

申请日：2007-07-11

Applicant: Hahn Vo Norden ,  Hubert E. Brinkmann ,  Paul V. Brownell ,  Kenneth T. Chin ,  James Dinh ,  David L. Matthews ,  Dwight D. Riley

Inventor： Hahn Vo Norden ,  Hubert E. Brinkmann ,  Paul V. Brownell ,  Kenneth T. Chin ,  James Dinh ,  David L. Matthews ,  Dwight D. Riley

IPC: H04L12/56 ,  H04L12/28

CPC classification number: H04L47/10 ,  H04L47/32 ,  H04L47/39

Abstract: A system is provided comprising a fabric coupling together a plurality of computing devices, wherein the fabric transfers a stream of packets between the computing devices. Each computing device comprises a Quality of Service (“QOS”) filter that monitors incoming packets to filter out packets of a maintenance type and permit transfer of packets of a transaction type.

Abstract translation: 提供了一种系统，其包括将多个计算设备耦合在一起的结构，其中该结构在计算设备之间传送分组流。 每个计算设备包括服务质量（“QOS”）过滤器，其监视进入的分组以过滤维护类型的分组并且允许传输交易类型的分组。

公开(公告)号：US07043656B2

公开(公告)日：2006-05-09

申请号：US10352711

申请日：2003-01-28

Applicant: Dwight D. Riley

Inventor： Dwight D. Riley

IPC: G06F1/04

CPC classification number: G06F13/4022

Abstract: Interconnect logic performs a transaction on an interconnect. The transaction may include multiple phases and the interconnect logic may include a counter state machine coupled to an interconnect state machine. The counter state machine may assert a signal to the interconnect state machine that may cause the interconnect state machine to prolong one or more phases of the transaction.

Abstract translation: 互连逻辑在互连上执行事务。 事务可以包括多个阶段，并且互连逻辑可以包括耦合到互连状态机的计数器状态机。 计数器状态机可以向互连状态机施加信号，这可能导致互连状态机延长交易的一个或多个阶段。

公开(公告)号：US06915446B2

公开(公告)日：2005-07-05

申请号：US09967612

申请日：2001-09-29

Applicant: Dwight D. Riley

Inventor： Dwight D. Riley

IPC: G06F11/00 ,  G06F11/08 ,  G06F11/10

CPC classification number: G06F11/10 ,  H04L1/0041 ,  H04L1/0071 ,  H04L1/0079 ,  H04L2001/0094

Abstract: An error correction code mechanism for the extensions to the peripheral component interconnect bus system (PCI-X) used in computer systems is fully backward compatible with the full PCI protocol. The error correction code check-bits can be inserted to provide error correction capability for the header address and attribute phases, as well as for burst and DWORD transaction data phases. The error correction code check-bits are inserted into unused attribute, clock phase, reserved, or reserved drive high portions of the AD and/or C/BE# lanes of the PCI-X phases.

Abstract translation: 用于计算机系统中的外设组件互连总线系统（PCI-X）扩展的纠错码机制与完整的PCI协议完全向后兼容。 可以插入纠错码校验位，以提供头部地址和属性相位以及突发和DWORD事务数据阶段的纠错能力。 错误校正码校验位被插入到PCI-X阶段的AD和/或C / BE＃通道的未使用的属性，时钟相位，保留或保留的驱动器高部分中。

公开(公告)号：US06892259B2

公开(公告)日：2005-05-10

申请号：US09967608

申请日：2001-09-29

Applicant: Alan L. Goodrum ,  Dwight D. Riley

Inventor： Alan L. Goodrum ,  Dwight D. Riley

IPC: G06F13/364 ,  G06F12/00 ,  G06F13/14 ,  G06F13/38

CPC classification number: G06F13/364

Abstract: A target device in a computer bus system allocates resources by selecting a priority requester for allocation of scarce resources. In a non-bus arbiter configuration, the first initiator device to receive a retry response to a transaction request after the resources are exhausted is designated as a priority requester. In a bus arbiter configuration, the priority requester is chosen on a round-robin basis from initiator devices that received a retry response to the initiator's most recent transaction request. If only one resource is available when an initiator sends a transaction request, the initiator receives a retry response unless the initiator is the priority requester.

Abstract translation: 计算机总线系统中的目标设备通过选择用于分配稀缺资源的优先级请求者来分配资源。 在非总线仲裁器配置中，在资源耗尽之后接收对事务请求的重试响应的第一启动器设备被指定为优先级请求器。 在总线仲裁器配置中，优先级请求者是从接收到对发起者最近的事务请求的重试响应的发起者设备的循环选择的。 如果发起方发送事务请求只有一个资源可用，则启动器将接收重试响应，除非启动器是优先级请求者。

公开(公告)号：US06871248B2

公开(公告)日：2005-03-22

申请号：US09967606

申请日：2001-09-29

Applicant: Dwight D. Riley

Inventor： Dwight D. Riley

IPC: G06F13/40 ,  G06F13/42 ,  G06F15/16 ,  H04J3/16 ,  H04J3/22

CPC classification number: G06F13/405

Abstract: An isochronous channel is configured on an interconnect bus between a first device and a second device. A first device requests an isochronous channel, required bandwidth, and a required service window size. If a service window of the required size at the required bandwidth is available, an isochronous bus controller sends the request to the second device. If the second device has a service window of the required size at the required, it accepts the isochronous channel request. The isochronous bus controller can be a collection of isochronous controllers, each controlling a subset of the interconnect bus. The isochronous bus controller then allocates bandwidth to the first device, notifying the first device to begin generating isochronous transactions, controlling access to the bus to ensure the first device does not exceed the bandwidth allocation. Further, the isochronous bus controller terminates the isochronous channel, if the first device stops sending isochronous transactions.

Abstract translation: 在第一设备和第二设备之间的互连总线上配置同步信道。 第一个设备请求同步信道，所需带宽和所需的服务窗口大小。 如果所需带宽的所需大小的服务窗口可用，则同步总线控制器将请求发送到第二设备。 如果第二个设备具有所需大小的服务窗口，则接受同步信道请求。 同步总线控制器可以是同步控制器的集合，每个控制器控制互连总线的子集。 等时总线控制器然后将带宽分配给第一设备，通知第一设备开始生成等时事务，控制对总线的访问以确保第一设备不超过带宽分配。 此外，等时总线控制器终止同步信道，如果第一设备停止发送同步事务。

公开(公告)号：US5954809A

公开(公告)日：1999-09-21

申请号：US684412

申请日：1996-07-19

Applicant: Dwight D. Riley ,  James R. Edwards ,  David J. Maguire

Inventor： Dwight D. Riley ,  James R. Edwards ,  David J. Maguire

IPC: G06F13/362 ,  G06F13/368

CPC classification number: G06F13/368

Abstract: An arbitration scheme for a computer system having multiple arbiters for arbitrating access to a plurality of buses. In the preferred embodiment, a computer system is divided into a detachable laptop portion and an expansion base unit coupled through a shared PCI bus. Each of the two portions of the computer system includes separate PCI arbitration circuitry for arbitrating requests for the PCI bus from potential PCI and ISA bus masters. Included within the laptop portion of the computer system is a top level arbiter that determines whether the PCI arbiter in the laptop or expansion base unit has access to the PCI bus. Either PCI arbiter normally must receive a grant from the top level arbiter before it runs a cycle. While the laptop computer is docked, the top level arbiter selects between the PCI arbiters on an essentially time multiplexed basis. While the expansion base and laptop computer are undocked, the top level arbiter grants bus access to the laptop PCI arbiter.

Abstract translation: 一种用于具有多个仲裁器的计算机系统的仲裁方案，用于仲裁对多条总线的访问。 在优选实施例中，计算机系统被分为可拆卸笔记本电脑部分和通过共享PCI总线耦合的扩展基座单元。 计算机系统的两个部分中的每一个包括单独的PCI仲裁电路，用于从潜在的PCI和ISA总线主机仲裁PCI总线的请求。 包括在计算机系统的笔记本电脑部分内的是顶级仲裁器，其确定膝上型计算机或扩展基座单元中的PCI仲裁器是否可以访问PCI总线。 PCI仲裁器通常必须在运行一个周期之前从顶级仲裁器接收授权。 当笔记本电脑停靠时，顶级仲裁器基本上基于时间复用的方式在PCI仲裁器之间进行选择。 当扩展基座和笔记本电脑脱离时，顶级仲裁器授予公共汽车访问笔记本电脑PCI仲裁器的权限。

公开(公告)号：US5937173A

公开(公告)日：1999-08-10

申请号：US873420

申请日：1997-06-12

Applicant: Sompong Paul Olarig ,  Dwight D. Riley ,  Ronald Timothy Horan

Inventor： Sompong Paul Olarig ,  Dwight D. Riley ,  Ronald Timothy Horan

IPC: G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4027

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between an additional registered peripheral component interconnect ("RegPCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional RegPCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional registered PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional registered PCI bus. Selection of the type of bus bridge (AGP or RegPCI) in the multiple use core logic chip set may be made by a hardware signal input, or by software during computer system configuration or power on self test ("POST"). Software configuration may also be determined upon detection of either an AGP or a RegPCI device connected to the common AGP/RegPCI bus.

Abstract translation: 在可以被配置为加速图形端口（“AGP”）总线与主机与存储器总线之间的桥接的计算机系统中提供了多用途核心逻辑芯片组，作为附加的注册的外围组件互连（“ RegPCI“）总线和主机和内存总线，或作为主PCI总线和附加RegPCI总线之间的桥梁。 多用途芯片组的功能是在计算机系统的制造时或在现场确定是否要实现AGP总线桥接器或附加的注册PCI总线桥接器。 多用核心逻辑芯片组具有仲裁器，其具有针对在附加的已注册PCI总线上使用的每个PCI设备的请求（“REQ”）和Grant（“GNT”）信号线。 可以通过硬件信号输入或在计算机系统配置或上电自检（“POST”）期间通过软件来选择多用途核心逻辑芯片组中的总线桥（AGP或RegPCI）的类型。 也可以在检测到连接到公共AGP / RegPCI总线的AGP或RegPCI设备时确定软件配置。