公开(公告)号：US20130059968A1

公开(公告)日：2013-03-07

申请号：US13596353

申请日：2012-08-28

申请人： Fei-Lin YANG ,  Yang-Po Chiu ,  Ching-Feng Chen ,  Po-Wen Huang ,  Chun-Kai Chou ,  Wun-Sheng Wu ,  Win-Jon Lin ,  Ping-Huang Chen

发明人： Fei-Lin YANG ,  Yang-Po Chiu ,  Ching-Feng Chen ,  Po-Wen Huang ,  Chun-Kai Chou ,  Wun-Sheng Wu ,  Win-Jon Lin ,  Ping-Huang Chen

IPC分类号： C08L67/02 ,  C08K3/04 ,  C08K3/40

CPC分类号： C08L67/02 ,  C08K7/04 ,  C08K7/14 ,  C08L77/02 ,  C08L81/04

摘要： The plastic composition includes PET and Nylon. The weight percentage of PET is between 20% and 90%. The weight percentage of Nylon is between 5% and 40%.

摘要翻译： 塑料成分包括PET和尼龙。 PET的重量百分比在20％至90％之间。 尼龙的重量百分比在5％至40％之间。

公开(公告)号：US20130022162A1

公开(公告)日：2013-01-24

申请号：US13186076

申请日：2011-07-19

申请人： Chan-Fei Lin ,  Shih-Chun Lin

发明人： Chan-Fei Lin ,  Shih-Chun Lin

IPC分类号： H04L7/00

CPC分类号： H03L7/07 ,  H03K5/135 ,  H03L7/0812

摘要： A multi-phase clock generator including a first delay locked loop, a reference signal generator and a second delay locked loop is provided. The first delay locked loop generates 2N phase clock signals according to an input clock signal, so as to equally divide a clock period of the input clock signal into 2N predetermined phases, where N is a positive integer. The reference signal generator selects two phase clock signals according to a digital signal, and adjusts an output ratio of the two phase clock signals in 2M clock periods to serve as a reference clock signal. The second delay locked loop delays a first phase clock signal according to a phase difference between the reference clock signal and an output clock signal. In this way, each predetermined phase is further equally divided into 2M sub-phases, so that the multi-phase clock generator has 2(N+M) phase selections.

摘要翻译： 提供了包括第一延迟锁定环路，参考信号发生器和第二延迟锁定环路的多相时钟发生器。 第一延迟锁定环根据输入时钟信号产生2N个相位时钟信号，以便将输入时钟信号的时钟周期等分成2N个预定相位，其中N是正整数。 参考信号发生器根据数字信号选择两相时钟信号，并在2M个时钟周期内调整两相时钟信号的输出比，作为参考时钟信号。 第二延迟锁定环根据参考时钟信号和输出时钟信号之间的相位差延迟第一相位时钟信号。 以这种方式，每个预定相位被进一步等分成2M个子相，使得多相时钟发生器具有2（N + M）个相位选择。

公开(公告)号：US20120212121A1

公开(公告)日：2012-08-23

申请号：US13242763

申请日：2011-09-23

申请人： Wen-Fei LIN

发明人： Wen-Fei LIN

IPC分类号： H01J61/06

CPC分类号： H01J9/18 ,  H01J61/0675 ,  H01J61/78

摘要： The present invention provides a ceramic-glass composite electrode and a fluorescent lamp having the same. The ceramic-glass composite electrode according to the present invention is a ceramic-glass composite, which is disposed at the ends of a glass tube of the fluorescent lamp. A stopper is disposed at the end of the glass tube for pushing against the ceramic-glass composite electrode and limiting the position of the ceramic-glass composite electrode slipped on the glass tube. Thereby, flowing of adhesives into the glass tube is avoided when the adhesives are used for gluing the glass tube and the ceramic-glass composite electrode, and hence extending the lifetime of the fluorescent lamp.

摘要翻译： 本发明提供一种陶瓷 - 玻璃复合电极和具有该电极的荧光灯。 根据本发明的陶瓷玻璃复合电极是设置在荧光灯的玻璃管的端部的陶瓷玻璃复合体。 在玻璃管的端部设置有用于推压陶瓷玻璃复合电极并限制滑动在玻璃管上的陶瓷 - 玻璃复合电极的位置的塞子。 因此，当粘合剂用于胶合玻璃管和陶瓷 - 玻璃复合电极，从而延长荧光灯的寿命时，可以避免粘合剂流入玻璃管中。

公开(公告)号：US20110255867A1

公开(公告)日：2011-10-20

申请号：US12759886

申请日：2010-04-14

申请人： Wen-Teng Fan ,  Chan-Fei Lin ,  Shih-Chun Lin

发明人： Wen-Teng Fan ,  Chan-Fei Lin ,  Shih-Chun Lin

IPC分类号： H04J14/00

CPC分类号： H03K5/135 ,  H03K2005/00052 ,  H03L7/0812

摘要： A phase selector including a plurality of buffers, a multiplexer, a first inverter, and a selecting circuit is provided. Each of the buffers provides a clock signal, and the clock signals have different phases. The multiplexer selectively outputs one of the clock signals as a switch signal according to a first control signal, wherein the first control signal is first portion of bits of a selecting signal. The input terminal of the first inverter receives a second control signal, wherein the second control signal is second portion of bits of the selecting signal, and the output terminal of the first inverter outputs an inverted signal. The selecting circuit transmits the second control signal of the selecting signal or the inverted signal to the output terminal of the phase selector according to the logic state of the switch signal.

摘要翻译： 提供了包括多个缓冲器的相位选择器，多路复用器，第一反相器和选择电路。 每个缓冲器提供时钟信号，并且时钟信号具有不同的相位。 复用器根据第一控制信号选择性地输出其中一个时钟信号作为开关信号，其中第一控制信号是选择信号的位的第一部分。 第一反相器的输入端接收第二控制信号，其中第二控制信号是选择信号的位的第二部分，第一反相器的输出端输出反相信号。 选择电路根据开关信号的逻辑状态将选择信号或反相信号的第二控制信号发送到相位选择器的输出端。

公开(公告)号：US20080180181A1

公开(公告)日：2008-07-31

申请号：US11669944

申请日：2007-01-31

申请人： Ming-Hung Wang ,  Peng-Fei Lin ,  Ming-Chi Lin

发明人： Ming-Hung Wang ,  Peng-Fei Lin ,  Ming-Chi Lin

IPC分类号： H03B27/00

CPC分类号： H03B27/00 ,  H03K5/13 ,  H03K2005/00052

摘要： An apparatus for generating multi-phase clock signals with a ring oscillator is provided, including a first stage phase-blender module and a second stage phase-blender module. The first stage phase-blender module further includes a plurality of differential OP phase-blender circuits. Each differential blender circuit has two signal inputs, and an output signal whose phase is an interpolation of the two input signal. The second stage phase blender module includes a plurality of inverter phase-blender circuits. Each inverter phase-blender circuit receives two output signals from the first stage phase-blender module as inputs, and outputs a clock signal with the interpolated phase of the two output signals of the first stage phase-blender module. The present invention also provides a method for generating multi-phase clock signals with a ring oscillator, including the following steps: (1) using a ring oscillator to provide at least two non-full swing signals, (2) using an differential OP phase-blender circuit to blend the phases of two non-full signals from the ring oscillator, and (3) using an inverter phase-blender circuit to generate multi-phase clock signal with interpolated phase.

摘要翻译： 提供了一种用于产生具有环形振荡器的多相时钟信号的装置，包括第一级相位 - 混合器模块和第二级相位 - 混合器模块。 第一级相位 - 搅拌器模块还包括多个差动OP相 - 搅拌器回路。 每个差分式混合器电路都有两个信号输入端，一个输出信号的相位是两个输入信号的插值。 第二级相位混合器模块包括多个逆变器相位混合器电路。 每个逆变器相位混合器电路接收来自第一级相位 - 混合器模块的两个输出信号作为输入，并且输出具有第一级相位 - 混合器模块的两个输出信号的内插相位的时钟信号。 本发明还提供了一种用环形振荡器产生多相时钟信号的方法，包括以下步骤：（1）使用环形振荡器提供至少两个非全摆幅信号，（2）使用差分OP相位 混合来自环形振荡器的两个非满信号的相位，以及（3）使用逆变器相位混合器电路产生具有内插相位的多相时钟信号。

公开(公告)号：US20080041758A1

公开(公告)日：2008-02-21

申请号：US11504594

申请日：2006-08-16

申请人： Yen-Fei Lin ,  Hui-Wen Chou ,  Wen-Yu Ku ,  Pu-Fang Chen ,  Tung-Li Lee ,  Jih-Hwa Wang

发明人： Yen-Fei Lin ,  Hui-Wen Chou ,  Wen-Yu Ku ,  Pu-Fang Chen ,  Tung-Li Lee ,  Jih-Hwa Wang

IPC分类号： B65D85/00

CPC分类号： H01L21/67366 ,  H01L21/67393

摘要： A wafer carrier. The wafer carrier includes a container and a plate, wherein the container has an inner wall and the plate is disposed in the vicinity of the inner wall of an upper portion of the container.

摘要翻译： 晶圆载体。 晶片载体包括容器和板，其中所述容器具有内壁，并且所述板设置在所述容器的上部的内壁附近。

公开(公告)号：US20050233481A1

公开(公告)日：2005-10-20

申请号：US11157571

申请日：2005-06-21

申请人： Yen-Fei Lin ,  Yueh-mao Sun ,  Wei-Jen Wen

发明人： Yen-Fei Lin ,  Yueh-mao Sun ,  Wei-Jen Wen

IPC分类号： G01R31/26 ,  H01L21/321 ,  H01L21/469

CPC分类号： H01L21/321 ,  H01L22/26

摘要： A method of fabricating a stabilized TiN control wafer comprising the following steps. A silicon substrate is provided having a silicon oxide layer formed thereover. An initial TiN layer is formed over the silicon oxide layer. The silicon substrate is placed in an atmosphere having ambient oxygen for from about 22 to 26 hours to form a rested TiN layer. The rested TiN layer is heated at a temperature of from about 115 to 125° C. for from about 85 to 95 seconds to form a heat treated TiN layer, whereby the heat treated TiN layer is stabilized to form the stabilized TiN control wafer.

摘要翻译： 一种制造稳定的TiN控制晶片的方法，包括以下步骤。 提供硅基板，其上形成有氧化硅层。 在氧化硅层上形成初始TiN层。 将硅衬底放置在具有环境氧的气氛中约22至26小时以形成静止的TiN层。 将该TiN层在约115〜125℃的温度下加热约85〜95秒，形成热处理TiN层，由此使经热处理的TiN层稳定，形成稳定的TiN对照晶片。

公开(公告)号：US5877635A

公开(公告)日：1999-03-02

申请号：US812430

申请日：1997-03-07

申请人： Perng-Fei Lin

发明人： Perng-Fei Lin

IPC分类号： H03K19/003 ,  H03K19/0185

CPC分类号： H03K19/00315

摘要： A buffer circuit for generating full-swing output is disclosed. The circuit includes a pull-up circuit for transferring a supply voltage to an output line in response to a first state of an input signal. A pull-down circuit is used to pull the output line down to a ground in response to a second state of the input signal. A control circuit is used to activate only one of the pull-up circuit and the pull-down circuit respectively in response to the first state and the second state of the input signal. Further, a charge-pump circuit responsive to the input signal and a clock signal is used to generate a charge-pump voltage to an input of the pull-up circuit so that the supply voltage is transferred to the output line.

摘要翻译： 公开了一种用于产生全摆幅输出的缓冲电路。 电路包括用于响应于输入信号的第一状态将电源电压传送到输出线的上拉电路。 下拉电路用于响应输入信号的第二状态将输出线向下拉到地。 控制电路用于响应于输入信号的第一状态和第二状态分别仅激活上拉电路和下拉电路中的一个。 此外，使用响应于输入信号和时钟信号的电荷泵电路来向上拉电路的输入产生电荷泵电压，使得电源电压被传送到输出线。

公开(公告)号：USD922378S1

公开(公告)日：2021-06-15

申请号：US29755342

申请日：2020-10-20

申请人： Fei Lin

设计人： Fei Lin

公开(公告)号：US20140171619A1

公开(公告)日：2014-06-19

申请号：US14122903

申请日：2012-05-25

申请人： Matthew Becker ,  Matthew Graham ,  Frank Harris ,  Fei Lin

发明人： Matthew Becker ,  Matthew Graham ,  Frank Harris ,  Fei Lin

IPC分类号： C07K7/06

CPC分类号： C07K7/06 ,  C07K7/08

摘要： A method for creating a peptide crosslinked bioactive polymeric material includes reacting a hydroxy-functionalized small molecule with a amino acid to form an amino acid functionalized monomer, reacting the amino acid functionalized monomer with a urea bond former to form a amino acid-based poly(ester urea), and reacting the amino acid-based poly(ester urea) with a peptide based crosslinker to form the peptide crosslinked bioactive polymeric material.

摘要翻译： 用于产生肽交联的生物活性聚合物材料的方法包括使羟基官能化的小分子与氨基酸反应以形成氨基酸官能化单体，使氨基酸官能化单体与脲键形成物反应形成基于氨基酸的聚（ 酯脲），并使基于氨基酸的聚（酯尿素）与基于肽的交联剂反应以形成肽交联的生物活性聚合物材料。