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公开(公告)号：US06388940B1
公开(公告)日：2002-05-14
申请号：US09672177
申请日：2000-09-27
IPC分类号： G11C800
CPC分类号： G11C7/12 , G11C11/419
摘要： A novel circuit technique for reducing leakage currents through the read-path of large register files in which a negative gate-source voltage is forced on a critical pass transistor between a cell read transistor and a local bitline such that when the cell is in a first state, the leakage current from a dynamic node of the cell read transistor is reduced. The reduced leakage current increases the robustness and performance of the read operation.
摘要翻译： 一种新颖的电路技术，用于减小通过大寄存器堆的读路径的漏电流，其中在栅极读取晶体管和局部位线之间的临界传输晶体管上施加负栅极 - 源极电压，使得当单元处于第一 状态，来自单元读取晶体管的动态节点的漏电流减小。 减小的漏电流增加了读操作的鲁棒性和性能。
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公开(公告)号：US20210119710A1
公开(公告)日：2021-04-22
申请号：US17133360
申请日：2020-12-23
申请人： Meer Nazmus Sakib , Peicheng Liao , Ranjeet Kumar , Duanni Huang , Haisheng Rong , Harel Frish , John Heck , Chaoxuan Ma , Hao Li , Ganesh Balamurugan
发明人： Meer Nazmus Sakib , Peicheng Liao , Ranjeet Kumar , Duanni Huang , Haisheng Rong , Harel Frish , John Heck , Chaoxuan Ma , Hao Li , Ganesh Balamurugan
IPC分类号： H04B10/61
摘要： Embodiments described herein may be related to apparatuses, processes, and techniques related to coherent optical receivers, including coherent receivers with integrated all-silicon waveguide photodetectors and tunable local oscillators implemented within CMOS technology. Embodiments are also directed to tunable silicon hybrid lasers with integrated temperature sensors to control wavelength. Embodiments are also directed to post-process phase correction of optical hybrid and nested I/Q modulators. Embodiments are also directed to demultiplexing photodetectors based on multiple microrings. In embodiments, all components may be implements on a silicon substrate. Other embodiments may be described and/or claimed.
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13.发明申请公开(公告)号：US20190033630A1
公开(公告)日：2019-01-31
申请号：US15834954
申请日：2017-12-07
申请人： Taehwan Kim , Ganesh Balamurugan , Hao Li , Hasitha Jayatilleka
发明人： Taehwan Kim , Ganesh Balamurugan , Hao Li , Hasitha Jayatilleka
IPC分类号： G02F1/01
摘要： Embodiments include apparatuses, methods, and systems including a dynamic polarization controller (DPC) to receive a first light beam and a second light beam, to adjust a rotation of a state of polarization (SOP) of the first light beam and the second light beam to generate a third light beam and a fourth light beam, under the control of a first control signal, a second control signal, and a third control signal. The first control signal may be related to a phase difference between the third light beam and the fourth light beam, the second control signal may be related to an intensity difference between the third light beam and the fourth light beam, and the third control signal may be related to a rotation of a SOP of the third light beam and the fourth light beam. Other embodiments may also be described and claimed.
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公开(公告)号：US09384163B2
公开(公告)日：2016-07-05
申请号：US13995110
申请日：2011-12-22
CPC分类号： G06F13/4086 , G06F13/14 , G06F13/36 , Y02D10/14 , Y02D10/151
摘要： An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines arc matched.
摘要翻译： 一个封装接口。 第一组第一组单端发射机电路。 第二组芯片上的第一组单端接收器电路。 接收器电路具有包括反相器和电阻反馈元件的终端电路。 多条导线耦合第一组发射机电路和第一组接收机电路。 多个导线的长度匹配。
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公开(公告)号：US08375242B2
公开(公告)日：2013-02-12
申请号：US13196871
申请日：2011-08-02
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译： 公开了用于时钟和数据恢复的方法和装置的实施例。 在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。 也可以公开和要求保护附加的变型和实施例。
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公开(公告)号：US20110289341A1
公开(公告)日：2011-11-24
申请号：US13196871
申请日：2011-08-02
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译： 公开了用于时钟和数据恢复的方法和装置的实施例。 在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。 也可以公开和要求保护附加的变型和实施例。
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公开(公告)号：US20090327788A1
公开(公告)日：2009-12-31
申请号：US12165428
申请日：2008-06-30
IPC分类号： G06F1/12
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译： 公开了用于时钟和数据恢复的方法和装置的实施例。 在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。 也可以公开和要求保护附加的变型和实施例。
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18.发明授权公开(公告)号：US07529296B2
公开(公告)日：2009-05-05
申请号：US11232492
申请日：2005-09-21
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L2025/03598 , H04L2025/03681
摘要： In some embodiments disclosed herein, equalizers in a receiver are adapted during normal operation, as they extract bit data from a received bit stream, to account for channel and/or circuit fluctuations.
摘要翻译： 在本文公开的一些实施例中，接收机中的均衡器在正常操作期间被适配，因为它们从接收到的比特流中提取比特数据，以解决信道和/或电路波动。
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公开(公告)号：US07313181B2
公开(公告)日：2007-12-25
申请号：US10660415
申请日：2003-09-10
CPC分类号： H04L25/03038 , H03H21/0001 , H03H2021/0065 , H04L2025/03477
摘要： An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: h(t+1)= h(t)+μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{ x(t)}, where h(t) is the filter vector representing the filter taps of the FIR filter, x(t) is the data vector representing present and past samples of the received data x(t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, μ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.
摘要翻译： 用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中通过执行更新的电路在训练序列期间迭代地更新滤波器：
h（t + 1 ）= h（t）+ mu [sgn {d（t-sgn {z（t）-Kd（t）sgn { x（t）}， 其中 h（t）是表示FIR滤波器的滤波器抽头的滤波器向量， x（t）是表示接收到的当前和过去样本的数据向量 数据x（t），d（t）是用于训练的期望数据，z（t）是FIR滤波器的输出，μ确定适配的存储器或窗口大小，K是考虑到的比例因子 通信信道，接收机和均衡器的实际限制。此外，提供了用于校准比例因子K的过程和电路结构。 -
公开(公告)号：US07275004B2
公开(公告)日：2007-09-25
申请号：US10743349
申请日：2003-12-23
IPC分类号： G06F19/00
CPC分类号： H03K5/19
摘要： An integrated circuit is provided that includes a first port to receive a first signal from a first channel and a first device coupled to the first port to modify a channel response of the first signal received from the first channel. A waveform capture device may be coupled to the first device to capture a waveform of a signal modified by the first device.
摘要翻译： 提供一种集成电路，其包括从第一信道接收第一信号的第一端口和耦合到第一端口的第一设备，以修改从第一信道接收到的第一信号的信道响应。 波形捕获装置可以耦合到第一装置以捕获由第一装置修改的信号的波形。
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