公开(公告)号：US06847650B1

公开(公告)日：2005-01-25

申请号：US09607066

申请日：2000-06-29

申请人： Glen D. Stone ,  David V. James ,  Bruce A. Fairman

发明人： Glen D. Stone ,  David V. James ,  Bruce A. Fairman

IPC分类号： G06F12/00 ,  H04L12/28 ,  H04L12/40 ,  H04L12/64

CPC分类号： H04L12/40058 ,  H04L12/40117 ,  H04L12/6418

摘要： A system and method for utilizing a memory device to support isochronous processes comprises a memory device that may be partitioned to provide an isochronous memory for storing high-priority isochronous information, and a processor device for accessing and utilizing the isochronous information that is stored in the isochronous memory. The isochronous memory is reserved for storing the isochronous information, and may be reconfigured into a selectable number of memory channels of varying size that each corresponds to an associated isochronous process.

摘要翻译： 一种利用存储器件来支持同步过程的系统和方法包括可被分区以提供用于存储高优先级等时信息的同步存储器的存储器设备，以及用于访问和利用存储在该等时信息中的等时信息的处理器设备 同步存储器 保留同步存储器用于存储同步信息，并且可以将其重新配置为可选数量的不同大小的存储器通道，每个存储器通道对应于相关联的同步过程。

公开(公告)号：USRE38514E1

公开(公告)日：2004-05-11

申请号：US09836314

申请日：2001-04-18

申请人： David V. James ,  Glen D. Stone

发明人： David V. James ,  Glen D. Stone

IPC分类号： G06F1200

CPC分类号： G06F12/0817

摘要： A system for controlling memory accesses in a memory device in a multi-processor computer system comprises a memory controller and a data storage. The data storage comprises a plurality of memory lines. Each memory line has a check field for storing a GONE code that indicates that the data is held in a cache, a g bit field for storing a G bit for confirming the code in the check field, a tag field for storing an identification of the processor in whose cache the data is held, and a d bit field for storing the true value of the G bit in rare situations. The memory controller comprises a data buffer, an address buffer, and a memory sequencer. The memory sequencer is a state machine for controlling the functions of the memory device. The method includes the steps of reading a memory line; determining if the data contained in a check field portion of the memory line matches a GONE code generated from the address of the memory line; if the check field and GONE code values do not match, reading the data as data; if the check field and GONE match, checking the G bit; if the G bit is 1, outputting the address of the processor that holds the data in its cache; and if the G bit is 0, reconstructing the data from a D bit and outputting the data as data.

公开(公告)号：US06438633B1

公开(公告)日：2002-08-20

申请号：US09553304

申请日：2000-04-20

申请人： Glen D. Stone

发明人： Glen D. Stone

IPC分类号： G06F1300

CPC分类号： G06F13/364

摘要： A system for providing deterministic performance from a non-deterministic device comprises one or more nodes that perform isochronous and/or non-isochronous data transfer operations onto an input/output bus of an electronic device. A bandwidth manager preferably programs a deterministic interface with a maximum data value that is selected to prevent non-isochronous conflicts for control of the input/output bus to thereby permit successfully execution of deterministically-scheduled isochronous data transfers. The deterministic interface preferably may interrupt a non-isochronous data transfer operation whenever a data-unit total from transferred data equals the corresponding programmed maximum data value. An interrupted node may then attempt to complete the non-isochronous data transfer operation in subsequent isochronous cycles.

摘要翻译： 用于从非确定性设备提供确定性性能的系统包括在电子设备的输入/输出总线上执行等时和/或非同步数据传输操作的一个或多个节点。 带宽管理器优选地以具有最大数据值的确定性接口来编程，所述最大数据值被选择以防止用于控制输入/输出总线的非等时冲突，从而允许成功执行确定性调度的同步数据传输。 每当来自传送数据的数据单元总数等于对应的编程的最大数据值时，确定性接口优选地可以中断非等时数据传送操作。 然后，中断的节点可以尝试在随后的同步周期中完成非同步数据传输操作。

公开(公告)号：US6108739A

公开(公告)日：2000-08-22

申请号：US301865

申请日：1999-04-29

申请人： David V. James ,  Donald N. North ,  Glen D. Stone

发明人： David V. James ,  Donald N. North ,  Glen D. Stone

IPC分类号： G06F13/40 ,  G06F13/36

CPC分类号： G06F13/4036

摘要： A system and method for avoiding starvation and deadlocks in a split-response-bus multiprocessor computer system. The multiprocessor computer system includes a first node and a second node coupled to the a split-response bus, wherein the first and second nodes communicate by passing request packets over the split-response bus. The method and system includes providing precedence information in the request packets, and then using the precedence information when receiving the request packets to determine which request packets to process and which request packets to reject when a conflict occurs.

摘要翻译： 一种用于避免分组响应总线多处理器计算机系统中的饥饿和死锁的系统和方法。 多处理器计算机系统包括耦合到分离响应总线的第一节点和第二节点，其中第一节点和第二节点通过在分组响应总线上传递请求分组进行通信。 所述方法和系统包括在请求分组中提供优先级信息，然后在接收到请求分组时使用优先级信息来确定要处理的请求分组以及当发生冲突时拒绝哪个请求分组。

公开(公告)号：US5323426A

公开(公告)日：1994-06-21

申请号：US839973

申请日：1992-02-21

申请人： David V. James ,  Donald N. North ,  Glen D. Stone

发明人： David V. James ,  Donald N. North ,  Glen D. Stone

IPC分类号： G06F5/06 ,  H04J3/07 ,  H04L7/00

CPC分类号： G06F5/06 ,  H04J3/07

摘要： An elasticity buffer for use in a data transmission system having a transmitter and a receiver and utilizing a data transfer protocol that periodically supplies an elasticity element that can be deleted or replicated by the elasticity buffer to maintain the synchronous transfer of data elements. The elasticity buffer includes: a memory array and at least one flag per memory location operative to be set to a first or second state; a write controller operating at the transmitter clock for writing the data elements into the memory locations in a sequential order and setting the corresponding flags; a read controller operating at the receiver clock for reading the data elements from the memory locations in the sequential order; and a flag controller for reading the flags, determining if the transmitter clock is faster or slower than the receiver clock from the pattern of flags read from memory, communicating a delete signal to the read controller to delete an elastic symbol if the transmitter clock leads the receiver clock, and communicating a replicate signal to the read controller if the transmitter clock lags the receiver.

摘要翻译： 一种在具有发射机和接收机的数据传输系统中使用的弹性缓冲器，并且利用周期性地提供可由弹性缓冲器删除或复制的弹性元件以维持数据元素的同步传输的数据传输协议。 弹性缓冲器包括：存储器阵列和每个存储器位置的至少一个标志，其可操作地被设置为第一或第二状态; 在发射机时钟处操作的写控制器，用于以顺序的顺序将数据元素写入存储器位置并设置相应的标志; 在接收器时钟处操作的读取控制器，用于以顺序从存储器位置读取数据元素; 以及用于读取标志的标志控制器，根据从存储器读取的标志图案确定发送器时钟是否比接收器时钟更快或更慢，如果发送器时钟引导到传送器时钟，则将删除信号传送到读取控制器以删除弹性符号 接收机时钟，并且如果发射机时钟滞后于接收机，则将复制信号传送到读控制器。

公开(公告)号：US07069558B1

公开(公告)日：2006-06-27

申请号：US09634213

申请日：2000-08-09

申请人： Glen D. Stone ,  Bruce A Fairman ,  Harold A. Ludtke

发明人： Glen D. Stone ,  Bruce A Fairman ,  Harold A. Ludtke

IPC分类号： G06F9/46

CPC分类号： G06F9/485 ,  G06F9/5016 ,  G06F9/5022 ,  G06F2209/482

摘要： A system and method for interactively utilizing a user interface to manage device resources comprises at least one resource characterization that includes resource requirements for executing a requested process. An allocation manager may then compare the resource requirements for the requested process to the currently-available device resources. The allocation manager may then authorize or deny the requested process depending upon whether the currently-available resources are sufficient to adequately service the resource requirements of the requested process. An interface manager may provide relevant information from sources such as the resource characterization and the allocation manager to a user interface to thereby allow a system user to interactively manage device resources.

公开(公告)号：US06578109B1

公开(公告)日：2003-06-10

申请号：US09606813

申请日：2000-06-29

申请人： Glen D. Stone ,  Scott D. Smyers ,  Bruce A. Fairman

发明人： Glen D. Stone ,  Scott D. Smyers ,  Bruce A. Fairman

IPC分类号： G06F1200

CPC分类号： G06F12/0842 ,  G06F12/121

摘要： A system and method for effectively implementing isochronous processor cache comprises a memory device for storing high-priority isochronous information, an isochronous cache coupled to the memory device for locally caching the isochronous information from the memory device, and a processor device for accessing and utilizing the isochronous information that is stored in the isochronous cache. The isochronous cache is reserved for storing the isochronous information, and may be reconfigured into a selectable number of cache channels of varying size that each corresponds to an associated isochronous process.

公开(公告)号：US6141212A

公开(公告)日：2000-10-31

申请号：US800057

申请日：1997-02-14

申请人： Peter W. Fletcher ,  Glen D. Stone

发明人： Peter W. Fletcher ,  Glen D. Stone

IPC分类号： G06F13/40 ,  H01R27/00 ,  G06F1/16 ,  H05K7/02

CPC分类号： G06F13/409 ,  H01R27/00 ,  H01R2201/04 ,  H01R2201/06

摘要： A multiple function peripheral connecting device that allows more functionality in the limited port space of a computer is disclosed. The connecting device provides the capability for external devices having different functions to be connected to the computer through a single port. This is accomplished by wiring a first function, internal to the computer, to certain pins of a modular connector, and wiring a second function, also internal to the computer, to a certain different combination of pins on the same modular connector. Because differently sized plugs can fit with the modular connector, peripherals associated with different types of systems can connect with the computer through the same single jack. Also, an adapter may be connected to the computer to allow simultaneous use of the two internal functions.

摘要翻译： 公开了一种在计算机的有限端口空间中允许更多功能的多功能外围设备连接装置。 连接设备提供具有不同功能的外部设备通过单个端口连接到计算机的能力。 这通过将计算机内部的第一功能连接到模块化连接器的某些引脚，并将第二功能（也在计算机内部）连接到同一模块化连接器上的特定不同组合的引脚来实现。 由于不同尺寸的插头可以与模块化连接器配合使用，与不同类型系统相关的外围设备可以通过相同的单个插孔与计算机连接。 此外，适配器可以连接到计算机以允许同时使用两个内部功能。

公开(公告)号：US5961623A

公开(公告)日：1999-10-05

申请号：US705324

申请日：1996-08-29

申请人： David V. James ,  Donald N. North ,  Glen D. Stone

发明人： David V. James ,  Donald N. North ,  Glen D. Stone

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4036

摘要： A system and method for avoiding starvation and deadlocks in a split-response-bus multiprocessor computer system. The multiprocessor computer system includes a first node and a second node coupled to the a split-response bus, wherein the first and second nodes communicate by passing request packets over the split-response bus. The method and system includes providing precedence information in the request packets, and then using the precedence information when receiving the request packets to determine which request packets to process and which request packets to reject when a conflict occurs.

公开(公告)号：US5895496A

公开(公告)日：1999-04-20

申请号：US972559

申请日：1997-11-18

申请人： David V. James ,  Glen D. Stone

发明人： David V. James ,  Glen D. Stone

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0817

摘要： A system for controlling memory accesses in a memory device in a multi-processor computer system comprises a memory controller and a data storage. The data storage comprises a plurality of memory lines. Each memory line has a check field for storing a GONE code that indicates that the data is held in a cache, a g bit field for storing a G bit for confirming the code in the check field, a tag field for storing an identification of the processor in whose cache the data is held, and a d bit field for storing the true value of the G bit in rare situations. The memory controller comprises a data buffer, an address buffer, and a memory sequencer. The memory sequencer is a state machine for controlling the functions of the memory device. The method includes the steps of reading a memory line; determining if the data contained in a check field portion of the memory line matches a GONE code generated from the address of the memory line; if the check field and GONE code values do not match, reading the data as data; if the check field and GONE match, checking the G bit; if the G bit is 1, outputting the address of the processor that holds the data in its cache; and if the G bit is 0, reconstructing the data from a D bit and outputting the data as data.

摘要翻译： 用于控制多处理器计算机系统中的存储器设备中的存储器访问的系统包括存储器控制器和数据存储器。 数据存储包括多条存储线。 每个存储器线具有用于存储指示数据被保存在高速缓存中的GONE代码的检查字段，用于存储用于确认校验字段中的代码的G位的标识字段，用于存储处理器的标识的标签字段 在其缓存中保存数据，以及广告位字段用于在极少数情况下存储G位的真实值。 存储器控制器包括数据缓冲器，地址缓冲器和存储器定序器。 存储器定序器是用于控制存储器件的功能的状态机。 该方法包括读取存储器线的步骤; 确定包含在存储器线的检查字段部分中的数据是否与从存储器线的地址生成的GONE代码相匹配; 如果检查字段和GONE代码值不匹配，则将数据读取为数据; 如果检查字段和GONE匹配，检查G位; 如果G位为1，则将保存数据的处理器的地址输出到其高速缓存中; 并且如果G位为0，则从D位重构数据并输出数据作为数据。