公开(公告)号：US6141212A

公开(公告)日：2000-10-31

申请号：US800057

申请日：1997-02-14

申请人： Peter W. Fletcher ,  Glen D. Stone

发明人： Peter W. Fletcher ,  Glen D. Stone

IPC分类号： G06F13/40 ,  H01R27/00 ,  G06F1/16 ,  H05K7/02

CPC分类号： G06F13/409 ,  H01R27/00 ,  H01R2201/04 ,  H01R2201/06

摘要： A multiple function peripheral connecting device that allows more functionality in the limited port space of a computer is disclosed. The connecting device provides the capability for external devices having different functions to be connected to the computer through a single port. This is accomplished by wiring a first function, internal to the computer, to certain pins of a modular connector, and wiring a second function, also internal to the computer, to a certain different combination of pins on the same modular connector. Because differently sized plugs can fit with the modular connector, peripherals associated with different types of systems can connect with the computer through the same single jack. Also, an adapter may be connected to the computer to allow simultaneous use of the two internal functions.

摘要翻译： 公开了一种在计算机的有限端口空间中允许更多功能的多功能外围设备连接装置。 连接设备提供具有不同功能的外部设备通过单个端口连接到计算机的能力。 这通过将计算机内部的第一功能连接到模块化连接器的某些引脚，并将第二功能（也在计算机内部）连接到同一模块化连接器上的特定不同组合的引脚来实现。 由于不同尺寸的插头可以与模块化连接器配合使用，与不同类型系统相关的外围设备可以通过相同的单个插孔与计算机连接。 此外，适配器可以连接到计算机以允许同时使用两个内部功能。

公开(公告)号：US07318090B1

公开(公告)日：2008-01-08

申请号：US09661226

申请日：2000-09-13

申请人： Bruce A Fairman ,  Glen D. Stone ,  Scott D. Smyers

发明人： Bruce A Fairman ,  Glen D. Stone ,  Scott D. Smyers

IPC分类号： G06F15/173 ,  G06F3/00 ,  G06F9/46

CPC分类号： G06F9/462

摘要： A method for utilizing concurrent context switching to support isochronous processes preferably comprises a main context that is configured to support system execution tasks, a first concurrent context that supports a first set of concurrent execution and loading procedures, and a second concurrent context that supports a second set of concurrent execution and loading procedures. A context control module preferably manages switching and loading procedures between the main context, the first concurrent context, and the second concurrent context. The context control module may perform successive concurrent context switching procedures by alternating between the first concurrent context and the second concurrent context to thereby sequentially support any desired number of isochronous processes.

摘要翻译： 一种利用并行上下文切换来支持同步进程的方法优选地包括被配置为支持系统执行任务的主上下文，支持第一组并行执行和加载过程的第一并发上下文以及支持第二并发上下文的第二并发上下文 一组并发执行和加载过程。 上下文控制模块优选地管理主上下文，第一并发上下文和第二并发上下文之间的切换和加载过程。 上下文控制模块可以通过在第一并发上下文和第二并发上下文之间交替来执行连续的并行上下文切换过程，从而顺序地支持任何期望数量的等时进程。

公开(公告)号：US5860080A

公开(公告)日：1999-01-12

申请号：US618628

申请日：1996-03-19

申请人： David V. James ,  Glen D. Stone

发明人： David V. James ,  Glen D. Stone

IPC分类号： G06F12/06 ,  G06F12/00

CPC分类号： G06F12/0669

摘要： A system and method for multicasting control signals to selectively operate one memory device or groups of memory devices comprises a memory controller coupled to a plurality of memory devices by a command bus and a data bus. Each of the plurality of memory devices has a unique identification number. The system provides an addressing scheme in which an individual memory device or groups of memory device can be selected for operation by addressing the devices with a command packet. The memory controller broadcasts a command packet over the command bus to the plurality of memory devices. The packet includes an identification number. At each of the memory devices, selection logic is included to make the memory device operational if the identification number in the packet matches the identification number assigned to the memory device. The address in the packet is preferably encoded such that identification number has the same size regardless of whether a single memory device is being selected for operation or a group of memory devices are being selected for operation. The present invention also includes a method for selecting groups of memory devices for operation by multicasting a select address comprising the steps of: providing an memory identification number to each memory device, transmitting an memory device selection address, comparing the memory device selection address to the memory identification number, and asserting a signal to make the memory device operational if the memory device selection address and the memory identification number match.

摘要翻译： 用于组播控制信号以选择性地操作一个存储器设备或存储器设备组的系统和方法包括通过命令总线和数据总线耦合到多个存储器设备的存储器控​​制器。 多个存储器件中的每一个具有唯一的识别号。 该系统提供寻址方案，其中可以通过用命令分组寻址设备来选择单独的存储器设备或存储器设备组来进行操作。 存储器控制器通过命令总线向多个存储器设备广播命令分组。 分组包括标识号。 在每个存储器件中，包括选择逻辑以使得如果分组中的识别号符合分配给存储器件的识别号，存储器件就可操作。 分组中的地址优选地被编码，使得识别号具有相同的大小，而不管单个存储器件是被选择用于操作还是一组存储器件正被选择用于操作。 本发明还包括一种通过多播选择地址来选择存储设备组进行操作的方法，包括以下步骤：向每个存储设备提供存储器标识号，发送存储器设备选择地址，将存储器设备选择地址与 存储器标识号，并且如果存储器件选择地址和存储器标识号匹配，则断言使存储器件工作的信号。

公开(公告)号：US06453376B1

公开(公告)日：2002-09-17

申请号：US09521334

申请日：2000-03-09

申请人： Bruce A. Fairman ,  Scott D. Smyers ,  Harold A. Ludtke ,  Glen D. Stone

发明人： Bruce A. Fairman ,  Scott D. Smyers ,  Harold A. Ludtke ,  Glen D. Stone

IPC分类号： G06F1200

CPC分类号： G06F9/485 ,  G06F9/4881 ,  G06F2209/485

摘要： A method for implementing scheduling mechanisms with selectable resource modes comprises at least one resource characterization set that includes a plurality of resource characterizations that each have resource requirements for executing a requested process. The plurality of resource characterizations may include a most mode, a best mode, and a worst mode. An allocation manager may then select a resource mode, and compare the corresponding resource requirements for the requested process to the currently-available device resources. The allocation manager may then authorize or deny the requested process depending upon whether the currently-available resources are sufficient to adequately service the resource requirements of the requested process.

摘要翻译： 用于用可选资源模式实现调度机制的方法包括至少一个资源表征集合，其包括多个资源表征，每个资源表征都具有用于执行所请求的进程的资源需求。 多个资源表征可以包括大多数模式，最佳模式和最差模式。 然后，分配管理器可以选择资源模式，并将所请求进程的相应资源需求与当前可用的设备资源进行比较。 然后，分配管理器可以根据当前可用的资源是否足以充分地满足所请求进程的资源需求来授权或拒绝所请求的进程。

公开(公告)号：US06414971B1

公开(公告)日：2002-07-02

申请号：US09494753

申请日：2000-01-31

申请人： David V James ,  Glen D. Stone

发明人： David V James ,  Glen D. Stone

IPC分类号： H04J306

CPC分类号： H04L12/40058 ,  H04J3/0652 ,  H04J3/0682 ,  H04L12/40091 ,  H04L12/4625 ,  H04N21/23608 ,  H04N21/4344 ,  H04N21/8547

摘要： A system and method for delivering data packets in an electronic interconnect comprises a talker device that transmits one or more data packets over a transmission path to a listener device through one or more bus bridges that each couple adjacent busses in the electronic interconnect. Each data packet includes a time stamp that indicates when the corresponding data packet is scheduled for presentation to the listener device. An initial bus bridge preferably creates a marker packet that is propagated through the transmission path to record delay information corresponding to delay elements such as the intervening bus bridges. A final bus bridge may then utilize the delay information from the marker packet to update the time stamps of the data packets to thereby incorporate the total propagation delay of the transmission path.

摘要翻译： 用于在电子互连中传送数据分组的系统和方法包括通过传输路径将一个或多个数据分组发送到收听者设备的通话器设备，该通话器设备通过一个或多个在电子互连中连接相邻总线的总线桥接器。 每个数据分组包括时间戳，其指示何时调度相应的数据分组以呈现给收听设备。 初始总线桥优选地创建通过传输路径传播的标记分组，以记录对应于诸如中间总线桥之类的延迟元件的延迟信息。 然后，最终总线桥可以利用来自标记分组的延迟信息来更新数据分组的时间戳，从而并入传输路径的总传播延迟。

公开(公告)号：US5841989A

公开(公告)日：1998-11-24

申请号：US631634

申请日：1996-04-08

申请人： David V. James ,  Glen D. Stone

发明人： David V. James ,  Glen D. Stone

IPC分类号： H04L12/42 ,  H04L12/56 ,  G06F13/00

CPC分类号： H04L45/00 ,  H04L12/42

摘要： A method and system for efficiently routing data packets in a computer interconnect includes a plurality of nodes forming a ringlet, generally including two connections between each pair of nodes configured to allow communication in either direction between each pair of nodes. One sequence of such connections forms a run moving,-for example left-to-right between a series of nodes. The other sequence of connections forms a right-to-left run. Selected nodes are configured to provide two cross-over paths, each from one run to the other, so the two runs are linked to form a circle or ringlet. One or more selected nodes provide an optional connection between the two runs, thus allowing a fast path or short cut to the opposing run. A fast path may include a uni- or bidirectional cross through path in an intermediate node. In one preferred embodiment, a single node can provide both cross-over paths, but can also support a cross-between path for each run, allowing a packet to continue on the same run, rather than the default path that crosses over to the opposite run. The method and system includes data information in a packet that can be used to decide whether to switch the packet through a fast path or to let it continue on the "normal" path. Routing decisions are based on a path field within each packet. This field is updated when taking a faster path (for example, a cross-through or cross-between path). The update techniques allow data packet path lengths to be reduced, while also providing a packet-aging capability. A scrubber is provided to manage packet aging and to remove packets that have not been removed from the ringlet but are no longer useful.

摘要翻译： 用于在计算机互连中有效地路由数据分组的方法和系统包括形成小环的多个节点，通常包括被配置为允许在每对节点之间的任一方向进行通信的每对节点之间的两个连接。 这种连接的一个顺序形成运行移动，例如在一系列节点之间从左到右。 连接的其他顺序形成从右到左的运行。 所选节点被配置为提供两个交叉路径，每个从一个运行到另一个运行，因此两个运行链接形成一个圆圈或小环。 一个或多个所选择的节点在两个运行之间提供可选的连接，从而允许对相对运行的快速路径或快捷方式。 快速路径可以包括中间节点中的单向或双向交叉路径。 在一个优选实施例中，单个节点可以提供两个交叉路径，但是也可以支持每次运行的交叉路径，从而允许分组在相同的运行中继续，而不是跨过相反的默认路径 跑。 该方法和系统包括数据包中的数据信息，该数据信息可用于决定是通过快速路径切换数据包还是使其继续在“正常”路径上。 路由决定基于每个数据包中的路径字段。 当采取更快的路径（例如，跨路径或交叉路径）之间时，此字段将被更新。 更新技术允许减少数据包路径长度，同时还提供数据包老化功能。 提供了一个洗涤器来管理数据包老化，并删除尚未从小环中删除但不再有用的数据包。

公开(公告)号：US5829035A

公开(公告)日：1998-10-27

申请号：US941807

申请日：1997-10-03

申请人： David V. James ,  Glen D. Stone ,  Donald N. North

发明人： David V. James ,  Glen D. Stone ,  Donald N. North

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0817 ,  Y10S707/99952

摘要： A multi-processor computer system comprising a data storage device, a memory controller, and a plurality of processors. The data storage device has a plurality of memory lines, each memory line having a portion for alternatively storing data or, a set of GONE codes, a count value, and a processor identification code value. A memory controller coupled to the data storage alternatively stores and retrieves data or the GONE code, the count field value and the processor identification code value. At least one of the processors includes a cache memory and a cache memory controller. The cache memory controller compares a GONE code associated with the requested memory line with the contents of the requested memory line, and requests the contents of the requested memory line from a second of the processors in response to the comparison.

摘要翻译： 一种包括数据存储设备，存储器控制器和多个处理器的多处理器计算机系统。 数据存储装置具有多条存储线，每条存储线具有用于交替存储数据的部分，或一组GONE码，计数值和处理器识别码值。 耦合到数据存储器的存储器控​​制器交替地存储和检索数据或GONE代码，计数字段值和处理器识别码值。 至少一个处理器包括高速缓冲存储器和高速缓冲存储器控制器。 高速缓冲存储器控制器将与所请求的存储器行相关联的GONE代码与所请求的存储器行的内容进行比较，并且响应于该比较，从第二处理器请求所请求的存储器行的内容。

公开(公告)号：US06934781B2

公开(公告)日：2005-08-23

申请号：US10226025

申请日：2002-08-22

申请人： Glen D. Stone ,  Bruce A. Fairman ,  Scott D. Smyers

发明人： Glen D. Stone ,  Bruce A. Fairman ,  Scott D. Smyers

IPC分类号： G06F13/362 ,  G06F13/364 ,  H04L12/40 ,  H04L12/403 ,  H04L12/64

CPC分类号： H04L12/40058 ,  G06F13/364

摘要： A system and method for effectively performing isochronous data transfers comprises a network device including an input/output (I/O) bus that is coupled to an input/output (I/O) node and an isochronous-capable network interface. The network interface and the I/O node may send requests to an arbiter for control of the I/O bus to perform a data transfer operation. In accordance with the present invention, an arbiter filter is interposed between the arbiter and both the network interface and the I/O node to filter respective requests for control of the I/O bus. The network interface advantageously provides an isochronous request to the arbiter filter to thereby de-assert conflicting requests so that the network interface may effectively perform a time-sensitive isochronous data transfer.

摘要翻译： 用于有效执行等时数据传输的系统和方法包括网络设备，其包括耦合到输入/输出（I / O）节点和等时同步网络接口的输入/输出（I / O）总线。 网络接口和I / O节点可以向仲裁器发送请求以控制I / O总线以执行数据传输操作。 根据本发明，在仲裁器和网络接口和I / O节点之间插入一个仲裁器滤波器，以过滤各个I / O总线控制请求。 网络接口有利地向仲裁器过滤器提供同步请求，从而解除冲突请求，使得网络接口可以有效地执行时间敏感的等时数据传输。

公开(公告)号：US06847650B1

公开(公告)日：2005-01-25

申请号：US09607066

申请日：2000-06-29

申请人： Glen D. Stone ,  David V. James ,  Bruce A. Fairman

发明人： Glen D. Stone ,  David V. James ,  Bruce A. Fairman

IPC分类号： G06F12/00 ,  H04L12/28 ,  H04L12/40 ,  H04L12/64

CPC分类号： H04L12/40058 ,  H04L12/40117 ,  H04L12/6418

摘要： A system and method for utilizing a memory device to support isochronous processes comprises a memory device that may be partitioned to provide an isochronous memory for storing high-priority isochronous information, and a processor device for accessing and utilizing the isochronous information that is stored in the isochronous memory. The isochronous memory is reserved for storing the isochronous information, and may be reconfigured into a selectable number of memory channels of varying size that each corresponds to an associated isochronous process.

摘要翻译： 一种利用存储器件来支持同步过程的系统和方法包括可被分区以提供用于存储高优先级等时信息的同步存储器的存储器设备，以及用于访问和利用存储在该等时信息中的等时信息的处理器设备 同步存储器 保留同步存储器用于存储同步信息，并且可以将其重新配置为可选数量的不同大小的存储器通道，每个存储器通道对应于相关联的同步过程。

公开(公告)号：USRE38514E1

公开(公告)日：2004-05-11

申请号：US09836314

申请日：2001-04-18

申请人： David V. James ,  Glen D. Stone

发明人： David V. James ,  Glen D. Stone

IPC分类号： G06F1200

CPC分类号： G06F12/0817

摘要： A system for controlling memory accesses in a memory device in a multi-processor computer system comprises a memory controller and a data storage. The data storage comprises a plurality of memory lines. Each memory line has a check field for storing a GONE code that indicates that the data is held in a cache, a g bit field for storing a G bit for confirming the code in the check field, a tag field for storing an identification of the processor in whose cache the data is held, and a d bit field for storing the true value of the G bit in rare situations. The memory controller comprises a data buffer, an address buffer, and a memory sequencer. The memory sequencer is a state machine for controlling the functions of the memory device. The method includes the steps of reading a memory line; determining if the data contained in a check field portion of the memory line matches a GONE code generated from the address of the memory line; if the check field and GONE code values do not match, reading the data as data; if the check field and GONE match, checking the G bit; if the G bit is 1, outputting the address of the processor that holds the data in its cache; and if the G bit is 0, reconstructing the data from a D bit and outputting the data as data.