公开(公告)号：US08386881B2

公开(公告)日：2013-02-26

申请号：US13465624

申请日：2012-05-07

申请人： Shinichi Kanno ,  Hironori Uchikawa

发明人： Shinichi Kanno ,  Hironori Uchikawa

IPC分类号： H03M13/00

CPC分类号： H03M13/2906 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1068 ,  G06F13/1673 ,  G06F13/4068 ,  G11C29/52 ,  H03M13/03 ,  H03M13/29 ,  H03M13/35 ,  H03M13/6561 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

公开(公告)号：US08385117B2

公开(公告)日：2013-02-26

申请号：US13233530

申请日：2011-09-15

申请人： Kenji Sakurada ,  Hironori Uchikawa

发明人： Kenji Sakurada ,  Hironori Uchikawa

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C8/08

摘要： A memory card decodes three bits of data stored in one memory cell and belonging to different pages, each being a unit of reading, by iterative calculation using probability based on eight threshold voltage distributions. The memory card includes a word line controlling section configured to select one required to read 1-bit data belonging to one of the pages to be read from among seven voltage sets which are composed of seven reference voltages for hard bit reading and a plurality of intermediate voltages for soft bit reading and perform control to apply the voltages of the selected voltage set as read voltages to the memory cell, a log likelihood ratio table storing section, and a decoder configured to decode read data using a log likelihood ratio.

摘要翻译： 存储卡通过使用基于八个阈值电压分布的概率的迭代计算来解码存储在一个存储器单元中的三位数据，并且属于不同页面，每一页都是读取单元。 存储卡包括字线控制部，被配置为从由七个用于硬比特读取的参考电压和多个中间值组成的七个电压组中选择要读取属于要读取的一个页面的1位数据所需的一个 用于软位读取的电压，并且执行控制以将所设置的所选电压的电压设置为读取电压到存储器单元，对数似然比表存储部分和被配置为使用对数似然比来解码读取数据的解码器。

公开(公告)号：US08086932B2

公开(公告)日：2011-12-27

申请号：US12233673

申请日：2008-09-19

申请人： Hironori Uchikawa ,  Kohsuke Harada

发明人： Hironori Uchikawa ,  Kohsuke Harada

IPC分类号： H03M13/00

CPC分类号： H03M13/114 ,  H03M13/112 ,  H03M13/3738 ,  H03M13/658 ,  H03M13/6583

摘要： There is provided with a decoding apparatus for decoding a low-density parity check code defined by a parity check matrix, includes: a first operation unit configured to carry out a row operation for each row of the parity check matrix; a calculation unit configured to calculate a reliability coefficient with respect to establishment of a parity check equation defined by said each row, respectively; a second operation unit configured to carry out a column operation for said each row; and a controller configured to iteratively execute one set which includes respective processing by the first operation unit, the calculation unit and the second operation unit and omit the processing by the first operation unit and the calculation unit for a row for which the reliability coefficient has satisfied a threshold.

摘要翻译： 提供了一种用于解码由奇偶校验矩阵定义的低密度奇偶校验码的解码装置，包括：第一操作单元，被配置为对奇偶校验矩阵的每一行执行行操作; 计算单元，被配置为分别计算关于由所述每行定义的奇偶校验方程的建立的可靠性系数; 第二操作单元，被配置为对所述每行执行列操作; 以及控制器，被配置为迭代地执行包括由所述第一操作单元，所述计算单元和所述第二操作单元进行的各自处理的一组，并且省略由所述第一操作单元和所述计算单元对于所述可靠性系数满足的行的处理 一个门槛。

公开(公告)号：US08078940B2

公开(公告)日：2011-12-13

申请号：US11877287

申请日：2007-10-23

申请人： Hironori Uchikawa ,  Tatsuyuki Ishikawa ,  Mitsuaki Honma

发明人： Hironori Uchikawa ,  Tatsuyuki Ishikawa ,  Mitsuaki Honma

IPC分类号： G11C29/00

CPC分类号： G06F11/1068 ,  G11C2029/0411

摘要： A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculation algorithms for deriving a likelihood value about a stored data bit from a threshold value read out of the memory cell. An error correction unit executes error correction through iterative processing using the likelihood value obtained at the likelihood calculator. A likelihood calculator controller changes among the likelihood calculation algorithms in the likelihood calculator based on a certain value of the number of iterations in the iterative processing obtained from the error correction unit.

摘要翻译： 非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括能够根据阈值电压的变化存储信息的多个存储单元。 似然度计算器具有多个似然计算算法，用于从从存储单元读出的阈值中导出关于存储的数据位的似然值。 错误校正单元通过使用在似然度计算器获得的似然值的迭代处理执行纠错。 似然度计算器控制器根据从误差校正单元获得的迭代处理中的迭代次数的一定值，在似然度计算器中的似然计算算法中进行变化。

公开(公告)号：US20110197110A1

公开(公告)日：2011-08-11

申请号：US13090539

申请日：2011-04-20

申请人： Shinichi KANNO ,  Hironori Uchikawa

发明人： Shinichi KANNO ,  Hironori Uchikawa

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/2906 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1068 ,  G06F13/1673 ,  G06F13/4068 ,  G11C29/52 ,  H03M13/03 ,  H03M13/29 ,  H03M13/35 ,  H03M13/6561 ,  Y02D10/14 ,  Y02D10/151

摘要： A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

公开(公告)号：US20110083060A1

公开(公告)日：2011-04-07

申请号：US12796211

申请日：2010-06-08

申请人： Kenji Sakurada ,  Hironori Uchikawa

发明人： Kenji Sakurada ,  Hironori Uchikawa

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C29/00

摘要： A memory system in an embodiment having a host and a memory card, including: a plurality of semiconductor memory cells, each cell being configured to store N-bit coded data based on threshold voltage distributions; an LLR table storage section configured to store a first LLR table that consists of normal LLR data corresponding to predetermined threshold voltages and a second LLR table that consists of LLR data such that two LLRs at each location corresponding to each location in the first LLR table at which a sign is inverted between two adjacent LLRs are “0”; and a decoder configured to perform decoding processing through probability-based repeated calculations using an LLR.

摘要翻译： 具有主机和存储卡的实施例中的存储器系统包括：多个半导体存储器单元，每个单元被配置为基于阈值电压分布来存储N位编码数据; LLR表存储部分，被配置为存储由对应于预定阈值电压的正常LLR数据组成的第一LLR表和由LLR数据组成的第二LLR表，使得在与第一LLR表中的每个位置对应的每个位置处的两个LLR 两个相邻的LLR之间的符号被反转的是“0”; 以及解码器，被配置为使用LLR执行基于概率的重复计算的解码处理。

公开(公告)号：US07508704B2

公开(公告)日：2009-03-24

申请号：US11772563

申请日：2007-07-02

申请人： Mitsuaki Honma ,  Noboru Shibata ,  Hironori Uchikawa

发明人： Mitsuaki Honma ,  Noboru Shibata ,  Hironori Uchikawa

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G06F11/1072 ,  G11C2211/5646

摘要： In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit data read voltage is larger than an upper limit of one of plural threshold voltage distributions and smaller than a lower limit of another threshold voltage distribution. Furthermore, it applies a soft-value read voltage as a word line voltage to the word line. The soft-value read voltage is smaller than an upper limit of a threshold voltage distribution and larger than a lower limit thereof. The likelihood calculation circuit calculates likelihood of the plural-bit data stores in the memory cells based on the soft-value.

摘要翻译： 在存储单元阵列中，能够存储多位数据的存储单元被排列成矩阵。 位线控制电路连接到位线以控制位线。 字线控制电路将多位数据读取电压作为字线电压施加到字线。 多位数据读取电压大于多个阈值电压分布中的一个的上限，并且小于另一个阈值电压分布的下限。 此外，它将软值读取电压作为字线电压施加到字线。 软值读取电压小于阈值电压分布的上限并且大于其下限。 似然度计算电路基于软值来计算存储单元中的多位数据存储的可能性。

公开(公告)号：US20080123408A1

公开(公告)日：2008-05-29

申请号：US11772563

申请日：2007-07-02

申请人： Mitsuaki Honma ,  Noboru Shibata ,  Hironori Uchikawa

发明人： Mitsuaki Honma ,  Noboru Shibata ,  Hironori Uchikawa

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G06F11/1072 ,  G11C2211/5646

摘要： In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit data read voltage is larger than an upper limit of one of plural threshold voltage distributions and smaller than a lower limit of another threshold voltage distribution. Furthermore, it applies a soft-value read voltage as a word line voltage to the word line. The soft-value read voltage is smaller than an upper limit of a threshold voltage distribution and larger than a lower limit thereof. The likelihood calculation circuit calculates likelihood of the plural-bit data stores in the memory cells based on the soft-value.

摘要翻译： 在存储单元阵列中，能够存储多位数据的存储单元被排列成矩阵。 位线控制电路连接到位线以控制位线。 字线控制电路将多位数据读取电压作为字线电压施加到字线。 多位数据读取电压大于多个阈值电压分布中的一个的上限，并且小于另一个阈值电压分布的下限。 此外，它将软值读取电压作为字线电压施加到字线。 软值读取电压小于阈值电压分布的上限并且大于其下限。 似然度计算电路基于软值来计算存储单元中的多位数据存储的可能性。

公开(公告)号：US09264072B2

公开(公告)日：2016-02-16

申请号：US13727422

申请日：2012-12-26

申请人： Hironori Uchikawa

发明人： Hironori Uchikawa

IPC分类号： H03M13/11 ,  H03M13/13

CPC分类号： H03M13/1154 ,  H03M13/13

摘要： According to one embodiment, an encoding apparatus includes an encoding unit. The encoding unit encodes a data bit sequence to generate a codeword corresponding to a parity check matrix. The parity check matrix is based on a protograph. In the protograph, each of n check nodes of a first type is connected to n variable nodes of a first type by a total of at least one edge of a first type, and to n variable nodes of a second type by a total of at least two edges of a second type. In the protograph, each of n check nodes of a second type is connected to the n variable nodes of the second type by a total of r edges of a third type, and to n variable nodes of a third type by a total of g edges of a fourth type.

摘要翻译： 根据一个实施例，编码装置包括编码单元。 编码单元对数据比特序列进行编码以产生与奇偶校验矩阵相对应的码字。 奇偶校验矩阵基于原型图。 在原型图中，第一类型的n个校验节点中的每一个通过总共至少一个第一类型的边缘连接到第一类型的n个可变节点，并且通过总共连接到第二类型的n个可变节点 至少两个边缘的第二种类型。 在原型图中，第二类型的n个校验节点中的每一个通过总共第三类型的r个边缘连接到第二类型的n个可变节点，并且通过总共g个边缘连接到第三个类型的n个可变节点 第四种类型。

公开(公告)号：US08966351B2

公开(公告)日：2015-02-24

申请号：US13706663

申请日：2012-12-06

申请人： Hironori Uchikawa ,  Haruka Obata

发明人： Hironori Uchikawa ,  Haruka Obata

IPC分类号： H03M13/00 ,  H03M13/13 ,  H03M13/11

CPC分类号： H03M13/13 ,  H03M13/116 ,  H03M13/118 ,  H03M13/611

摘要： According to one embodiment, an encoding apparatus includes an input unit and a generation unit. The input unit inputs a data symbol sequence containing q(N−J) symbols (q, J, and N are integers, N>J). The generation unit generates a codeword containing qN symbols by adding a parity symbol sequence containing qJ symbols to the data symbol sequence. The codeword satisfies parity check equations of a parity check matrix of qJ rows×qN columns. A first submatrix of qJ rows×qJ columns that corresponds to the parity symbol sequence in the parity check matrix includes a second submatrix. The second submatrix includes a first identity matrix of qL rows×qL columns (L is an integer, J>L) and a first non-zero matrix of q(J−L) rows×qL columns.

摘要翻译： 根据一个实施例，编码装置包括输入单元和生成单元。 输入单元输入包含q（N-J）个符号（q，J和N是整数N> J）的数据符号序列。 生成单元通过将包含qJ个符号的奇偶校验符号序列添加到数据符号序列来生成包含qN符号的码字。 码字满足qJ行×qN列的奇偶校验矩阵的奇偶校验方程。 对应于奇偶校验矩阵中的奇偶校验符号序列的qJ行×qJ列的第一子矩阵包括第二子矩阵。 第二子矩阵包括qL行×qL列（L是整数J> L）和q（J-L）行×qL列的第一非零矩阵的第一单位矩阵。