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    LEAD FREE SOLDER ALLOY AND MANUFACTURING METHOD THEREOF
    13.
    发明申请
    LEAD FREE SOLDER ALLOY AND MANUFACTURING METHOD THEREOF 有权
    无铅焊接合金及其制造方法

    公开(公告)号：US20100272598A1

    公开(公告)日：2010-10-28

    申请号：US12309382

    申请日：2008-09-04

    Applicant: Kang Hee Kim ,  Yong Cheol Chu ,  Myoung Ho Chun ,  Sang Ho Jeon ,  Hyun Kyu Lee

    Inventor： Kang Hee Kim ,  Yong Cheol Chu ,  Myoung Ho Chun ,  Sang Ho Jeon ,  Hyun Kyu Lee

    IPC: C22C13/00 ,  C22C1/02

    CPC classification number: B23K35/262 ,  B23K35/40 ,  C22C1/02 ,  C22C13/00 ,  H05K3/3463

    Abstract: Disclosed herein are a lead-free solder alloy and a manufacturing method thereof. More specifically, disclosed are: a lead-free solder alloy, which comprises 0.8-1.2 wt % silver (Ag), 0.8-1.2 wt % copper (Cu), 0.01-1.0 wt % palladium (Pd), 0.001-0.1 wt % tellurium (Te), and a balance of tin (Sn), and thus has a melting point similar to those of prior lead-free solder alloys, excellent wettability, very low segregation ratio, and excellent weldability with a welding base metal, such that it improves temperature cycle performance and drop impact resistance simultaneously, when it is applied to electronic devices and printed circuit boards; a manufacturing method of the above alloy; and electronic devices and printed circuit boards which include the same.

    Abstract translation: 本发明公开了一种无铅焊料合金及其制造方法。 更具体地，公开了：无铅焊料合金，其包含0.8-1.2重量％的银（Ag），0.8-1.2重量％的铜（Cu），0.01-1.0重量％的钯（Pd），0.001-0.1重量％ 碲（Te）和锡（Sn）的平衡，因此具有与现有的无铅焊料合金相似的熔点，优异的润湿性，极低的偏析比和与焊接母材具有优异的焊接性，使得 当它应用于电子设备和印刷电路板时，同时提高温度循环性能和降低耐冲击性; 上述合金的制造方法; 以及包括其的电子设备和印刷电路板。

    Method and apparatus for inspecting flat panel display
    15.
    发明授权
    Method and apparatus for inspecting flat panel display 有权
    检查平板显示器的方法和装置

    公开(公告)号：US07301360B2

    公开(公告)日：2007-11-27

    申请号：US10669348

    申请日：2003-09-25

    Applicant: Jong Dam Kim ,  Hyun Kyu Lee ,  Yong Jin Cho ,  See Hwa Jeong

    Inventor： Jong Dam Kim ,  Hyun Kyu Lee ,  Yong Jin Cho ,  See Hwa Jeong

    IPC: G01R31/00

    CPC classification number: G09G3/006 ,  G01R31/315 ,  G09G3/3648 ,  G09G2300/0426

    Abstract: A novel method and apparatus inspects liquid crystal display. The method and apparatus for inspecting the flat display device scans at least one signal wire by using a magnetic sensor and detects a resistance change of the magnetic sensor to perceive a short in the signal wire. Pixels can be tested using an array of magnetic sensors configured such that each sensor in the array is smaller than the pixel.

    Abstract translation: 一种新颖的方法和装置检查液晶显示器。 用于检查平板显示装置的方法和装置通过使用磁传感器扫描至少一根信号线，并检测磁传感器的电阻变化以感知信号线中的短路。 可以使用配置为阵列中的每个传感器小于像素的磁性传感器阵列来测试像素。

    Array substrate for in-plane switching mode liquid crystal display device and method of manufacturing the same
    16.
    发明申请
    Array substrate for in-plane switching mode liquid crystal display device and method of manufacturing the same 有权
    用于面内切换模式液晶显示装置的阵列基板及其制造方法

    公开(公告)号：US20070153203A1

    公开(公告)日：2007-07-05

    申请号：US11643794

    申请日：2006-12-22

    Applicant: Eui-Tae Kim ,  Byoung-Ho Lim ,  Hyun-Kyu Lee ,  Sang-Wook Park

    Inventor： Eui-Tae Kim ,  Byoung-Ho Lim ,  Hyun-Kyu Lee ,  Sang-Wook Park

    IPC: G02F1/1343

    CPC classification number: G02F1/13439 ,  G02F2001/134372 ,  G02F2001/13629

    Abstract: An array substrate for an in-plane switching mode liquid crystal display device includes a substrate, a gate line along a first direction on the substrate, a data line along a second direction and crossing the gate line to define a pixel region, a thin film transistor connected to the gate and data lines, a pixel electrode in the pixel region and connected to the thin film transistor, and a common electrode in the pixel region and arranged in an alternating pattern with the pixel electrode, wherein each of the pixel electrode and the common electrode includes a transparent conductive pattern, and one of the pixel electrode and the common electrode further includes an opaque conductive pattern having a more narrow width than the transparent conductive pattern.

    Abstract translation: 面内切换模式液晶显示装置的阵列基板包括基板，沿着基板的第一方向的栅极线，沿着第二方向的数据线，与栅极线交叉以限定像素区域，薄膜 连接到栅极和数据线的晶体管，像素区域中的像素电极并连接到薄膜晶体管，以及像素区域中的公共电极，并且与像素电极交替排列，其中每个像素电极和 公共电极包括透明导电图案，并且像素电极和公共电极中的一个还包括具有比透明导电图案更窄的宽度的不透明导电图案。

    System and method for compensating timing error using pilot symbol in OFDM/CDMA communication system
    17.
    发明授权
    System and method for compensating timing error using pilot symbol in OFDM/CDMA communication system 有权
    在OFDM / CDMA通信系统中使用导频符号补偿定时误差的系统和方法

    公开(公告)号：US07110387B1

    公开(公告)日：2006-09-19

    申请号：US09677085

    申请日：2000-09-29

    Applicant: Hye-Jeong Kim ,  Hyun-Kyu Lee

    Inventor： Hye-Jeong Kim ,  Hyun-Kyu Lee

    IPC: H04B7/208

    CPC classification number: H04L27/2662 ,  H04L5/0016 ,  H04L5/0048 ,  H04L27/2656 ,  H04L27/2657 ,  H04L27/2675

    Abstract: A timing error compensation system in an OFMD/CDMA communication system includes an analog-to-digital converter for converting an OFDM signal, comprised of a data symbol stream in which a pilot symbol is inserted at intervals of a prescribed number of data symbols, received from a transmitter, to a digital OFDM symbol stream by prescribed sampling synchronization, a guard interval remover for removing a guard interval inserted in the OFDM symbol by prescribed frame synchronization, and a fast Fourier transform (FFT) device for performing fast Fourier transform on the guard interval-removed OFDM symbol and outputting a data symbol stream. In the time error compensation system, a pilot symbol detector receives the data symbol stream and detects the pilot symbols inserted in the data symbol stream at prescribed intervals. A timing compensator determines a linear phase difference line for the detected pilot symbol, generates a timing error estimation signal according to the determined linear phase difference line, and provides the timing error estimation signal to the analog-to-digital converter and the guard interval remover so as to determine the sampling synchronization and the frame synchronization.

    Abstract translation: OFMD / CDMA通信系统中的定时误差补偿系统包括：一个模数转换器，用于转换OFDM信号，该OFDM信号包括一个数据符号流，其中以接收的规定数量的数据符号的间隔插入导频符号 通过规定的采样同步从发射机到数字OFDM符号流;保护间隔去除器，用于通过规定的帧同步去除插入在OFDM符号中的保护间隔;以及快速傅里叶变换（FFT）装置，用于对 保护间隔去除的OFDM符号并输出数据符号流。 在时间误差补偿系统中，导频符号检测器接收数据符号流，并以规定的间隔检测插入在数据符号流中的导频符号。 定时补偿器确定检测到的导频符号的线性相位差线，根据确定的线性相位差线产生定时误差估计信号，并将定时误差估计信号提供给模数转换器和保护间隔去除器 以便确定采样同步和帧同步。

    Semiconductor device and method for controlling the same
    18.
    发明授权
    Semiconductor device and method for controlling the same 有权
    半导体装置及其控制方法

    公开(公告)号：US07054204B2

    公开(公告)日：2006-05-30

    申请号：US10828454

    申请日：2004-04-20

    Applicant: Jong-hyoung Lim ,  Hyuk-joon Kwon ,  Hyun-kyu Lee

    Inventor： Jong-hyoung Lim ,  Hyuk-joon Kwon ,  Hyun-kyu Lee

    IPC: G11C7/00 ,  G11C8/00

    CPC classification number: G11C11/4076 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/229

    Abstract: Disclosed herein are a semiconductor method and device which are capable of reducing data write errors by rewriting last write data during a write recovery time (tWR). The semiconductor device comprises a memory cell array consisting of a plurality of repetitive cell units; a bit line amplifier for amplifying a voltage difference between a bit line voltage and a complementary bit line voltage of the memory cell array; switching devices activated by a column selection line signal for electrically connecting a data line and a complementary data line to the bit line and the complementary bit line, respectively; and a write driver for supplying a write data voltage to the data line and the complementary data line, wherein the column selection line signal is generated during a write recovery time. The method for controlling the semiconductor device including a memory cell array having a plurality of repetitive cell units, a bit line amplifier for amplifying a voltage difference between a bit line voltage and a complementary bit line voltage of the memory cell array, switching devices activated by a column selection line signal for electrically connecting a data line and a complementary data line to the bit line and the complementary bit line, respectively, and a write driver for supplying a write data voltage to the data line and the complementary data line, comprises the steps of: writing data voltage into the memory cell array; and generating the column selection line signal during a write recovery time.

    Abstract translation: 这里公开了一种半导体方法和装置，其能够通过在写入恢复时间（tWR）期间重写最后写入数据来减少数据写入错误。 半导体器件包括由多个重复单元单元组成的存储单元阵列; 位线放大器，用于放大存储单元阵列的位线电压和互补位线电压之间的电压差; 由列选择线信号激活的开关装置，用于将数据线和互补数据线分别电连接到位线和互补位线; 以及用于向数据线和互补数据线提供写数据电压的写驱动器，其中在写恢复时间期间产生列选择线信号。 用于控制包括具有多个重复单元单元的存储单元阵列的半导体器件的方法，用于放大位线电压和存储单元阵列的互补位线电压之间的电压差的位线放大器，由 用于将数据线和互补数据线分别电连接到位线和互补位线的列选择线信号和用于向数据线和互补数据线提供写数据电压的写驱动器，包括： 步骤：将数据电压写入存储单元阵列; 以及在写恢复时间期间产生列选择线信号。

    Thin film transistor substrate and fabricating method thereof
    19.
    发明授权
    Thin film transistor substrate and fabricating method thereof 有权
    薄膜晶体管基板及其制造方法

    公开(公告)号：US06452210B2

    公开(公告)日：2002-09-17

    申请号：US09739823

    申请日：2000-12-20

    Applicant: Hyun Kyu Lee

    Inventor： Hyun Kyu Lee

    IPC: H01L2904

    CPC classification number: G02F1/1368 ,  G02F2001/133357 ,  G02F2001/136222 ,  H01L29/42384 ,  H01L29/78636

    Abstract: A thin film transistor substrate having a structure in which a thin film transistor array is formed on color filters. In the substrate, a thin film transistor is formed on the color filters. A smoothing layer compensates for step coverage between the color filters and is provided with a recess in which a gate electrode of the thin film transistor is to be formed. Accordingly, step coverage in the gate electrode is eliminated, so that it becomes possible to manufacture a large-dimension panel without a limitation to the thickness and profile of the gate electrode.

    Abstract translation: 具有薄膜晶体管阵列形成在滤色器上的结构的薄膜晶体管基板。 在衬底中，在滤色器上形成薄膜晶体管。 平滑层补偿滤色器之间的台阶覆盖，并且设置有要形成薄膜晶体管的栅电极的凹部。 因此，省去了栅电极中的台阶覆盖，使得可以制造大尺寸面板而不限制栅电极的厚度和轮廓。

    Frequency synchronizing device for OFDM/CDMA system
    20.
    发明授权
    Frequency synchronizing device for OFDM/CDMA system 失效
    OFDM / CDMA系统的频率同步装置

    公开(公告)号：US06373861B1

    公开(公告)日：2002-04-16

    申请号：US09452359

    申请日：1999-12-01

    Applicant: Hyun-Kyu Lee

    Inventor： Hyun-Kyu Lee

    IPC: H04J1100

    CPC classification number: H04L5/026 ,  H04L27/2659 ,  H04L27/266

    Abstract: A frequency synchronizing device for an OFDM/CDMA communication system which exchanges data using an OFDM frame including OFDM symbols each comprised of a plurality of data samples, and a guard interval inserted at the head of each symbol to prevent interference between the symbols. The frequency synchronizing device comprises a frequency corrector for compensating for a frequency offset of received analog data according to a frequency correction signal; an analog/digital converter for converting the received analog data to OFDM frame; and a frequency synchronizer for detecting copy data which is used for creating the guard interval from the OFDM frame and is comprised of some data samples out of the OFDM symbols, to sequentially estimate coarse, regular and fine frequency offsets, and providing the frequency corrector with the frequency correction signal corresponding to the estimated frequency offsets.

    Abstract translation: 一种用于OFDM / CDMA通信系统的频率同步装置，其使用包括每个由多个数据样本组成的OFDM符号的OFDM帧来交换数据，以及插入每个符号的头部的防护间隔，以防止符号之间的干扰。 频率同步装置包括：频率校正器，用于根据频率校正信号补偿接收到的模拟数据的频率偏移; 用于将接收到的模拟数据转换成OFDM帧的模拟/数字转换器; 以及频率同步器，用于检测用于从OFDM帧创建保护间隔的复制数据，并且由OFDM符号中的一些数据样本组成，以顺序地估计粗略的，规则的和精细的频率偏移，并且向频率校正器提供频率校正器 所述频率校正信号对应于估计的频率偏移。

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