公开(公告)号：US07412546B2

公开(公告)日：2008-08-12

申请号：US11320277

申请日：2005-12-27

Applicant: Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

Inventor： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC: G06F5/00 ,  G06F15/16

CPC classification number: H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

Abstract translation: 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。

公开(公告)号：US07395517B2

公开(公告)日：2008-07-01

申请号：US11230956

申请日：2005-09-20

Applicant: Fabrice Jean Verplanken ,  Jean-Paul Aldebert ,  Claude Basso ,  Jean Louis Calvignac

Inventor： Fabrice Jean Verplanken ,  Jean-Paul Aldebert ,  Claude Basso ,  Jean Louis Calvignac

IPC: G06F17/50

CPC classification number: H04L69/16 ,  H04L49/45 ,  H04L69/161

Abstract: A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.

Abstract translation: 公开了可重构计算环境中的数据对准器。 实施例使用现场可配置门阵列（FPGA）中的硬件宏来最小化移动数据字节所需的可配置逻辑块（CLB）的数量。 与专用集成电路相比，对准机制允许灵活性，可扩展性，可配置性和降低的成本。

公开(公告)号：US07376809B2

公开(公告)日：2008-05-20

申请号：US11076218

申请日：2005-03-09

Applicant: Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

Inventor： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

IPC: G06F12/02

CPC classification number: H04L49/901 ,  H04L49/252 ,  H04L49/30 ,  H04L49/90 ,  H04L69/12 ,  H04L69/22

Abstract: Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

Abstract translation: 公开了一种用于在网络处理器中实现多帧控制块的系统和方法。 实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。 随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。 帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。 网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。 每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。 由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

公开(公告)号：US07327759B2

公开(公告)日：2008-02-05

申请号：US09912781

申请日：2001-07-25

Applicant: Jean Louis Calvignac ,  Mohammad Peyravian ,  Fabrice Jean Verplanken

Inventor： Jean Louis Calvignac ,  Mohammad Peyravian ,  Fabrice Jean Verplanken

IPC: H04J3/24

CPC classification number: H04L49/9094 ,  H04L47/10 ,  H04L47/34 ,  H04L49/90 ,  H04L49/9089

Abstract: Packets or frames of data may be compressed, encrypted/decrypted, filtered, classified, searched or subjected to other deep-packet processing operations before being distributed through the internet. The microprocessor system and method of the present invention provide for the orderly processing of such data packets without disrupting or changing the sequence in which the data is intended to be transmitted to its destination. This is achieved by receiving frames into an input buffer for processing. Associated with this input buffer is a unit for determining the operation to be performed on each frame. An arbitrator assigns each frame to a processing core engine. An output buffer collects the processed frames, and a sequencer forwards the processed frames from the output buffer to their destination in the same order as received by the input/output buffer. Maintaining the sequence of data transmission is particularly useful in voice transmission, such as videos and movies.

Abstract translation: 数据包或数据帧可以在通过因特网分发之前被压缩，加密/解密，过滤，分类，搜索或经受其他深度包处理操作。 本发明的微处理器系统和方法提供这种数据分组的有序处理，而不会中断或改变数据要发送到其目的地的序列。 这通过将帧接收到用于处理的输入缓冲器中来实现。 与该输入缓冲器相关联的是用于确定要在每个帧上执行的操作的单元。 仲裁员将每个帧分配给处理核心引擎。 输出缓冲器收集经处理的帧，并且定序器按照输入/输出缓冲器接收的顺序将处理后的帧从输出缓冲区转发到其目的地。 保持数据传输的顺序在诸如视频和电影的语音传输中特别有用。

公开(公告)号：US07315901B1

公开(公告)日：2008-01-01

申请号：US09548913

申请日：2000-04-13

Applicant: Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

Inventor： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC: G06F15/173 ,  H04L12/24

CPC classification number: H04L47/522 ,  H04L47/2425 ,  H04L47/50 ,  H04L47/568 ,  H04L47/58 ,  H04L47/6235 ,  H04L47/6265

Abstract: A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. A system for allowing peak bursts based on a system of credits and charges is taught along limits on such peak bursts. Also taught is a system for preventing a flow's disconnection and reconnection to the queues from allowing it to unfairly achieve an improved position.

Abstract translation: 一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。 本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。 根据这种峰值突发的限制，教导了基于信用和费用系统允许峰值突发的系统。 还教导了一种用于防止流动断开和重新连接到队列的系统，从而允许其不公平地实现改进的位置。

公开(公告)号：US07200696B2

公开(公告)日：2007-04-03

申请号：US09828342

申请日：2001-04-06

Applicant: Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

Inventor： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC: G06F15/16

CPC classification number: H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

Abstract: A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes a plurality of control blocks, one for each data buffer, each containing control information to link one buffer to another for transmission. Each of the control blocks has a last bit feature which is a single bit and indicates when the data buffer having the last bit is transmitted. This last bit feature is a bit which can be set to either zero or one. The last bit feature is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit feature is communicated to the network processor to indicate whether the transmission of a particular frame is ended and a new frame is to be transmitted.

Abstract translation: 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括多个控制块，一个用于每个数据缓冲器，每个控制块包含用于将一个缓冲器链接到另一缓冲器以进行传输的控制信息。 每个控制块具有作为单个位的最后位特征，并且指示何时发送具有最后位的数据缓冲器。 这最后一位功能是一个可以设置为零或一个的位。 当附加数据缓冲器被链接到先前的数据缓冲器指示要发送附加数据缓冲器时，最后一位特征处于第一位置，而当没有附加数据缓冲器被链接到先前的数据缓冲器时，第二位置 。 将最后一位特征的位置传送给网络处理器，以指示特定帧的传输是否结束，并且要发送新的帧。

公开(公告)号：US07133931B1

公开(公告)日：2006-11-07

申请号：US09479026

申请日：2000-01-07

Applicant: Samuel Steven Allison ,  Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

Inventor： Samuel Steven Allison ,  Brian Mitchell Bass ,  Jean Louis Calvignac ,  Anthony Matteo Gallo ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC: G06F15/16 ,  G06F15/167 ,  H04B7/216 ,  H04L12/28

CPC classification number: H04L49/30 ,  H04L49/109

Abstract: A system and method of altering frames being processed by a network processing unit. The system includes a set of defined alterations, with some of the alterations being fixed alterations which are advantageously handled by hardware to accomplish the fixed alterations rapidly and without executing a stored program and other alterations which include a variable portion, with these variable alterations being accomplished through the use of stored programs allowing the variables to be used to effect variable alterations to a frame. The present system accommodates a change in the duration of life of a frame or information unit and addition or deletion of bits and also allows for a new cyclic redundancy checking to be accomplished for a revised information unit. Advantageously, the frame alteration system is on the same substrate as the processors.

Abstract translation: 一种改变由网络处理单元处理的帧的系统和方法。 该系统包括一组定义的改变，其中一些变化是固定的改变，其有利地被硬件处理以快速完成固定的变更，而不执行存储的程序和包括可变部分的其他改变，这些可变改变被完成 通过使用存储的程序，允许使用变量来实现对框架的变化。 本系统适应帧或信息单元的持续时间的改变以及比特的添加或删除，并且还允许为修改的信息单元完成新的循环冗余校验。 有利地，框架改变系统在与处理器相同的衬底上。

公开(公告)号：US07120630B2

公开(公告)日：2006-10-10

申请号：US10650397

申请日：2003-08-28

Applicant: Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

Inventor： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC: G06F7/00 ,  H04L12/56

CPC classification number: H04L45/742 ,  H04L45/7453 ,  Y10S707/99933 ,  Y10S707/99934 ,  Y10S707/99935 ,  Y10S707/99936 ,  Y10S707/99937 ,  Y10S707/99943 ,  Y10S707/99945

Abstract: Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key.

Abstract translation: 用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。 键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。 搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。 检索所需的两个密钥和相应的信息都存储在Patricia树结构中。 散列函数提供密钥的比特到散列密钥的比特的n> n映射。

公开(公告)号：US07089555B2

公开(公告)日：2006-08-08

申请号：US10179100

申请日：2002-06-25

Applicant: Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Steven Kenneth Jenkins ,  Ross Boyd Leavens ,  Robert Brian Likovich, Jr.

Inventor： Jean Louis Calvignac ,  Gordon Taylor Davis ,  Marco Heddes ,  Steven Kenneth Jenkins ,  Ross Boyd Leavens ,  Robert Brian Likovich, Jr.

IPC: G06F9/46 ,  G06F12/00

CPC classification number: G06F9/526

Abstract: An ordered semaphore management subsystem and method for use in an application system which includes a plurality of processors competing for shared resources each of which is controlled by a unique semaphore. The subsystem generates an ordered semaphore field (OSF) corresponding to each processor in a linked list of processors and assigns one of four statuses to the OSF depending on the position the processor occupies in the linked list of processors competing for the shared resources. The four states are (1) semaphore head (SH); (2) behind semaphore head (BSH); (3) semaphore head behind (SHB); and (4) skip (Skip). Only the SH processor is allocated the semaphore when requested. A processor not in the SH state will be denied the semaphore even if is available to assure sequential access.

公开(公告)号：US07085266B2

公开(公告)日：2006-08-01

申请号：US10095792

申请日：2002-03-12

Applicant: Jean Louis Calvignac ,  Marco Heddes ,  Joseph Franklin Logan

Inventor： Jean Louis Calvignac ,  Marco Heddes ,  Joseph Franklin Logan

IPC: H04L12/50

CPC classification number: G06F15/7825

Abstract: An interface to interconnect chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The chips can be configured in different operational modes which dictates what portion of a frame is to be transmitted between selected chips of the system.