Detection of a disturbance in a calculation performed by an integrated circuit
    11.
    发明授权
    Detection of a disturbance in a calculation performed by an integrated circuit 有权
    检测由集成电路执行的计算中的干扰

    公开(公告)号:US08150029B2

    公开(公告)日:2012-04-03

    申请号:US11647114

    申请日:2006-12-28

    CPC classification number: G06F7/723 G06F7/725 G06F2207/7261 G06F2207/7271

    Abstract: A method for detecting a disturbance of a calculation, by an electronic circuit, of a result of an integral number of applications of an internal composition law on elements of an abelian group, by successive iterations of different steps according to the even or odd character of a current coefficient of a polynomial representation of said integral number, the degree of which determines the number of iterations, each iteration including: in case of an odd current coefficient, updating at least one first variable intended to contain the result at the end of the calculation; and in case of an even current coefficient, of updating a second variable and a comparison of this second variable with an expected value.

    Abstract translation: 一种用于通过电子电路计算由abelian组的元素组成的内部组成定律的整体数量的结果的方法,通过根据偶数或奇数特征的不同步骤的连续迭代来检测 所述积分数的多项式表示的当前系数,其度数确定迭代次数,每次迭代包括:在奇数电流系数的情况下,更新旨在包含结果的结果的至少一个第一变量 计算; 并且在均匀电流系数的情况下,更新第二变量和将该第二变量与期望值的比较。

    VERIFICATION OF DATA READ IN MEMORY
    13.
    发明申请
    VERIFICATION OF DATA READ IN MEMORY 有权
    内存中数据读取的验证

    公开(公告)号:US20100325320A1

    公开(公告)日:2010-12-23

    申请号:US12743684

    申请日:2008-10-18

    CPC classification number: G06F21/606 G06F21/755

    Abstract: A method and a circuit for checking data transferred between a circuit and a processing unit, in which: the data originating from the circuit transit through a first buffer element having a size which is a multiple of the size of data to be subsequently delivered over a bus of the processing unit; an address provided by the processing unit for the circuit is temporarily stored in a second element; and the content of the first element is compared with current data originating from the circuit, at least when they correspond to an address of data already present in this first element.

    Abstract translation: 一种用于检查在电路和处理单元之间传送的数据的方法和电路,其中:从电路发出的数据通过第一缓冲元件,该第一缓冲元件的尺寸是要随后传送的数据的大小的倍数 总线处理单元; 由电路处理单元提供的地址暂时存储在第二元件中; 并且将第一元素的内容与来自电路的当前数据进行比较,至少当它们对应于已经存在于该第一元素中的数据的地址时。

    INTERFACE BETWEEN A TWIN-WIRE BUS AND A SINGLE-WIRE BUS
    14.
    发明申请
    INTERFACE BETWEEN A TWIN-WIRE BUS AND A SINGLE-WIRE BUS 有权
    双线总线和单线总线之间的接口

    公开(公告)号:US20100017553A1

    公开(公告)日:2010-01-21

    申请号:US12502634

    申请日:2009-07-14

    CPC classification number: G06F13/4282 G06F13/4027 G06F2213/0016

    Abstract: A method and a device for converting a first bus including at least a data wire and a clock wire into a single-wire bus, wherein a data bit of the first bus is converted on half a period of the clock signal for transmission over the second bus, a waiting pattern being placed on the second bus during the other half-period.

    Abstract translation: 一种用于将包括至少数据线和时钟线的第一总线转换成单线总线的方法和装置,其中第一总线的数据位在时钟信号的半个周期上被转换,以在第二总线上传输第二总线 公共汽车,在另一半期间,等待方式被放置在第二辆公共汽车上。

    Detection of a disturbance in a calculation performed by an integrated circuit
    15.
    发明申请
    Detection of a disturbance in a calculation performed by an integrated circuit 有权
    检测由集成电路执行的计算中的干扰

    公开(公告)号:US20080021941A1

    公开(公告)日:2008-01-24

    申请号:US11647114

    申请日:2006-12-28

    CPC classification number: G06F7/723 G06F7/725 G06F2207/7261 G06F2207/7271

    Abstract: A method for detecting a disturbance of a calculation, by an electronic circuit, of a result of an integral number of applications of an internal composition law on elements of an abelian group, by successive iterations of different steps according to the even or odd character of a current coefficient of a polynomial representation of said integral number, the degree of which determines the number of iterations, each iteration including: in case of an odd current coefficient, updating at least one first variable intended to contain the result at the end of the calculation; and in case of an even current coefficient, of updating a second variable and a comparison of this second variable with an expected value.

    Abstract translation: 一种用于通过电子电路计算由abelian组的元素组成的内部组成定律的整体数量的结果的方法,通过根据偶数或奇数特征的不同步骤的连续迭代来检测 所述积分数的多项式表示的当前系数,其度数确定迭代次数,每次迭代包括:在奇数电流系数的情况下,更新旨在包含结果的结果的至少一个第一变量 计算; 并且在均匀电流系数的情况下,更新第二变量和将该第二变量与期望值的比较。

    Integrated circuit test simulator
    16.
    发明申请
    Integrated circuit test simulator 审中-公开
    集成电路测试模拟器

    公开(公告)号:US20070083351A1

    公开(公告)日:2007-04-12

    申请号:US11546509

    申请日:2006-10-11

    CPC classification number: G01R31/318342

    Abstract: A method and a simulator for testing an electronic circuit by parallel execution of a program in the circuit and in a simulator, including a step of checking that commands and conditions contained in the simulator have effectively been executed during the test.

    Abstract translation: 一种用于通过并行执行电路和模拟器中的程序来测试电子电路的方法和仿真器,包括在测试期间有效地执行包含在模拟器中的命令和条件的步骤。

    Verification of data read in memory
    19.
    发明授权
    Verification of data read in memory 有权
    在内存中读取的数据的验证

    公开(公告)号:US08775697B2

    公开(公告)日:2014-07-08

    申请号:US12743684

    申请日:2008-10-18

    CPC classification number: G06F21/606 G06F21/755

    Abstract: A method and a circuit for checking data transferred between a circuit and a processing unit, in which: the data originating from the circuit transit through a first buffer element having a size which is a multiple of the size of data to be subsequently delivered over a bus of the processing unit; an address provided by the processing unit for the circuit is temporarily stored in a second element; and the content of the first element is compared with current data originating from the circuit, at least when they correspond to an address of data already present in this first element.

    Abstract translation: 一种用于检查在电路和处理单元之间传送的数据的方法和电路,其中:从电路发出的数据通过第一缓冲元件,该第一缓冲元件的尺寸是要随后传送的数据的大小的倍数 总线处理单元; 由电路处理单元提供的地址暂时存储在第二元件中; 并且将第一元素的内容与来自电路的当前数据进行比较,至少当它们对应于已经存在于该第一元素中的数据的地址时。

    Non-volatile memory counter
    20.
    发明授权
    Non-volatile memory counter 有权
    非易失性存储器计数器

    公开(公告)号:US08660233B2

    公开(公告)日:2014-02-25

    申请号:US13560476

    申请日:2012-07-27

    CPC classification number: H03K21/00 G11C16/349 H03K21/403

    Abstract: A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.

    Abstract translation: 包括至少两个子计数器的非易失性存储器中的计数器,每个副计数器以不同的模计数,在单个子计数器上传送的计数器的增量和子计数器依次递增。

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