公开(公告)号：US08386858B2

公开(公告)日：2013-02-26

申请号：US12616529

申请日：2009-11-11

申请人： Jeong-Hun Lee ,  Jeong-Tae Hwang

发明人： Jeong-Hun Lee ,  Jeong-Tae Hwang

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/46

摘要： A semiconductor memory device is capable of performing a test operation in its various operation modes. Particularly, the semiconductor memory device can enter a test mode in other modes, as well as, an all bank pre-charge mode. The semiconductor memory device includes a test mode control block configured to generate a test signal enabled for a predetermined interval in an active mode, and a mode register set control block configured to enable a mode register set signal for a test operation in the predetermined interval in response to the test signal.

摘要翻译： 半导体存储器件能够在其各种操作模式下执行测试操作。 特别地，半导体存储器件可以进入其他模式的测试模式以及全部银行预充电模式。 半导体存储器件包括：测试模式控制块，被配置为在激活模式下产生预定间隔使能的测试信号;以及模式寄存器组控制模块，被配置为使得模式寄存器设置信号能够在预定间隔内进行测试操作 响应测试信号。

公开(公告)号：US20120155203A1

公开(公告)日：2012-06-21

申请号：US13104262

申请日：2011-05-10

申请人： Jeong-Tae Hwang ,  Jeong-Hun Lee

发明人： Jeong-Tae Hwang ,  Jeong-Hun Lee

IPC分类号： G11C29/18

CPC分类号： G11C29/28

摘要： A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the addresses, the commands, the data, and the internal bank address, and providing the test device with a test result signal.

摘要翻译： 一种测试半导体存储器件的方法包括通过通道从测试设备接收时钟，地址，命令和数据，响应于地址和命令产生内部存储体地址，对每一个执行多位并行测试 基于地址，命令，数据和内部存储体地址的多个存储体，以及向测试装置提供测试结果信号。

公开(公告)号：US08958262B2

公开(公告)日：2015-02-17

申请号：US13334025

申请日：2011-12-21

申请人： Jeong-Tae Hwang

发明人： Jeong-Tae Hwang

IPC分类号： G11C8/00 ,  G11C8/12 ,  G11C8/06

CPC分类号： G11C8/12 ,  G11C8/06

摘要： A bank selection circuit includes a command latch unit configured to latch an input command at a time earlier than a rising edge of a clock by a setup time, a command decoder configured to decode a latched command and generate a row operation signal, a bank address latch unit configured to latch an input bank address at a time earlier than the rising edge of the clock by the setup time, a bank address decoder configured to decode a latched bank address and generate a bank selection signal, and a bank selection unit configured to receive the row operation signal and the bank selection signal and transfer the row operation signal to a bank selected by the bank selection signal.

摘要翻译： 存储体选择电路包括：命令锁存单元，被配置为在比时钟的上升沿更早的时间锁存输入命令建立时间;命令解码器，被配置为对锁存的命令进行解码并生成行操作信号， 锁存单元，被配置为在比所述建立时间的时钟的上升沿早的时间锁存输入存储体地址;存储体地址解码器，被配置为对锁存的存储体地址进行解码并产生存储体选择信号;以及存储体选择单元， 接收行操作信号和存储体选择信号，并将行操作信号传送到由存储体选择信号选择的存储体。

公开(公告)号：US08644106B2

公开(公告)日：2014-02-04

申请号：US13220983

申请日：2011-08-30

申请人： Jeong-Tae Hwang

发明人： Jeong-Tae Hwang

IPC分类号： G11C8/00

CPC分类号： G11C7/1072 ,  G11C7/109 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4093

摘要： A shift circuit of a semiconductor device reduces the power consumption of the semiconductor device. The shift circuit comprises a plurality of shifters and a plurality of clock controllers. The plurality of shifters shifts an input signal in sequence in response to a clock. The plurality of clock each supply the clock to a corresponding shifter before an input of the corresponding shifter is activated and stop the supply of the clock to the corresponding shifter when an output of the corresponding shifter is activated.

摘要翻译： 半导体器件的移位电路降低了半导体器件的功耗。 移位电路包括多个移位器和多个时钟控制器。 多个移位器响应于时钟顺序地移位输入信号。 在对应的移位器的输入被激活之前，多个时钟将时钟提供给相应的移位器，并且当对应的移位器的输出被激活时，停止向对应的移位器提供时钟。

公开(公告)号：US08503260B2

公开(公告)日：2013-08-06

申请号：US13104262

申请日：2011-05-10

申请人： Jeong-Tae Hwang ,  Jeong-Hun Lee

发明人： Jeong-Tae Hwang ,  Jeong-Hun Lee

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C29/28

摘要： A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the addresses, the commands, the data, and the internal bank address, and providing the test device with a test result signal.

摘要翻译： 一种测试半导体存储器件的方法包括通过通道从测试设备接收时钟，地址，命令和数据，响应于地址和命令产生内部存储体地址，对每一个执行多位并行测试 基于地址，命令，数据和内部存储体地址的多个存储体，以及向测试装置提供测试结果信号。

公开(公告)号：US20130003482A1

公开(公告)日：2013-01-03

申请号：US13525885

申请日：2012-06-18

申请人： Jeong-Tae HWANG

发明人： Jeong-Tae HWANG

IPC分类号： G11C7/00

CPC分类号： G11C11/40615 ,  G11C11/40611 ,  G11C2211/4067

摘要： An self-refresh control circuit for controlling a self-refresh operation of a memory device includes a self-refresh control logic block configured to control the memory device to perform the self-refresh operation and an initial refresh control block configured to activate the self-refresh control logic block in an initialization period of the memory device.

摘要翻译： 一种用于控制存储装置的自刷新操作的自刷新控制电路，包括配置成控制存储装置执行自刷新操作的自刷新控制逻辑块，以及配置为启动自刷新操作的初始刷新控制块， 在存储器件的初始化期间刷新控制逻辑块。

公开(公告)号：US20120269017A1

公开(公告)日：2012-10-25

申请号：US13302267

申请日：2011-11-22

申请人： Jeong-Tae HWANG

发明人： Jeong-Tae HWANG

IPC分类号： G11C7/22 ,  H03L7/00

CPC分类号： G11C7/222

摘要： A delay circuit includes a delay unit configured to generate a delayed transfer signal by delaying a transfer signal corresponding to a first signal or a second signal, a distinguishment signal generation unit configured to generate a distinguishment signal which represents to what signal the transfer signal correspond between the first signal and the second signal and a delayed signal generation unit configured to output the delayed transfer signal as a first delayed signal or a second delayed signal in response to the distinguishment signal.

摘要翻译： 延迟电路包括：延迟单元，被配置为通过延迟与第一信号或第二信号相对应的传送信号来产生延迟传送信号;区分信号生成单元，被配置为生成表示传送信号对应于哪个信号的区别信号 所述第一信号和所述第二信号以及延迟信号生成单元，被配置为响应于所述识别信号，将延迟的传送信号作为第一延迟信号或第二延迟信号输出。

公开(公告)号：US20120188839A1

公开(公告)日：2012-07-26

申请号：US13334025

申请日：2011-12-21

申请人： Jeong-Tae HWANG

发明人： Jeong-Tae HWANG

IPC分类号： G11C8/10

CPC分类号： G11C8/12 ,  G11C8/06

摘要： A bank selection circuit includes a command latch unit configured to latch an input command at a time earlier than a rising edge of a clock by a setup time, a command decoder configured to decode a latched command and generate a row operation signal, a bank address latch unit configured to latch an input bank address at a time earlier than the rising edge of the clock by the setup time, a bank address decoder configured to decode a latched bank address and generate a bank selection signal, and a bank selection unit configured to receive the row operation signal and the bank selection signal and transfer the row operation signal to a bank selected by the bank selection signal.

摘要翻译： 存储体选择电路包括：命令锁存单元，被配置为在比时钟的上升沿更早的时间锁存输入命令建立时间;命令解码器，被配置为对锁存的命令进行解码并生成行操作信号， 锁存单元，被配置为在比所述建立时间的时钟的上升沿早的时间锁存输入存储体地址;存储体地址解码器，被配置为对锁存的存储体地址进行解码并产生存储体选择信号;以及存储体选择单元， 接收行操作信号和存储体选择信号，并将行操作信号传送到由存储体选择信号选择的存储体。

公开(公告)号：US20120087200A1

公开(公告)日：2012-04-12

申请号：US13159821

申请日：2011-06-14

申请人： Sang Hee LEE ,  Jeong Tae HWANG

发明人： Sang Hee LEE ,  Jeong Tae HWANG

IPC分类号： G11C8/12 ,  G11C8/06

CPC分类号： G11C8/12 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/4094 ,  G11C2207/005

摘要： A semiconductor memory device includes first and second bank groups and an internal column address generating circuit. Each of the first and second bank groups includes at least one bank. The internal column address generating circuit converts a column address into a first internal column address and outputs the first internal column address through a first transmission line in response to a bank address if a read operation or a write operation is performed on a bank of the first bank group. Also, the internal column address generating circuit converts the column address into a second internal column address and outputs the second internal column address through a second transmission line in response to the bank address if a read operation or a write operation is performed on a bank of the second bank group.

摘要翻译： 半导体存储器件包括第一和第二组组以及内部列地址发生电路。 第一和第二银行组中的每一个包括至少一个银行。 内部列地址发生电路将列地址转换为第一内部列地址，并且如果对第一内部列地址的存储体执行读取操作或写入操作，则响应于存储体地址而通过第一传输线输出第一内部列地址 银行集团。 此外，内部列地址发生电路将列地址转换为第二内部列地址，并且如果对一行的行执行读取操作或写入操作，则响应于存储体地址而通过第二传输线输出第二内部列地址 第二银行集团。

公开(公告)号：US20120081100A1

公开(公告)日：2012-04-05

申请号：US12983090

申请日：2010-12-31

申请人： Jeong Hun LEE ,  Yong Mi KIM ,  Jeong Tae HWANG

发明人： Jeong Hun LEE ,  Yong Mi KIM ,  Jeong Tae HWANG

IPC分类号： G05F3/02

CPC分类号： G11C5/147 ,  G11C29/021

摘要： A semiconductor apparatus includes a comparison voltage generation unit configured to generate a plurality of different comparison voltages, a reference voltage generation unit configured to receive a generation code from an external system, select one of the plurality of the different comparison voltages according to the generation code, and generate a reference voltage, and a reference voltage determination unit configured to receive the generation code and an expected reference voltage from the external system, check whether a level of the expected reference voltage is in a target range, and output a check result to the external system.

摘要翻译： 一种半导体装置，包括：被配置为生成多个不同的比较电压的比较电压生成单元，被配置为从外部系统接收生成代码的基准电压生成单元，根据生成代码选择所述多个不同的比较电压中的一个 并产生参考电压，参考电压确定单元被配置为从外部系统接收生成代码和预期参考电压，检查预期参考电压的电平是否在目标范围内，并将检查结果输出到 外部系统。