公开(公告)号：US20070254444A1

公开(公告)日：2007-11-01

申请号：US11608591

申请日：2006-12-08

Applicant: Joe Bloomquist ,  Peter Javorka ,  Manfred Horstmann ,  Gert Burbach

Inventor： Joe Bloomquist ,  Peter Javorka ,  Manfred Horstmann ,  Gert Burbach

IPC: H01L29/80 ,  H01L21/336

CPC classification number: H01L21/84 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/1203 ,  H01L29/7843

Abstract: By selectively performing a pre-amorphization implantation process in logic areas and memory areas, the negative effect of the interaction between stressed overlayers and dislocation defects may be avoided or at least significantly reduced in the memory areas, thereby increasing production yield and stability of the memory areas.

Abstract translation: 通过在逻辑区域和存储区域中选择性地执行预非晶化注入工艺，可以避免在应力覆盖层和位错缺陷之间的相互作用的负面影响或至少在存储区域中显着降低，从而提高存储器的产量和稳定性 地区

公开(公告)号：US08274120B2

公开(公告)日：2012-09-25

申请号：US12710744

申请日：2010-02-23

Applicant: Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann ,  Peter Javorka ,  Joe Bloomquist

Inventor： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann ,  Peter Javorka ,  Joe Bloomquist

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L29/66628 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78621 ,  H01L29/78684

Abstract: By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism.

Abstract translation: 通过凹陷漏极和源极区域，可以在凹部中形成诸如接触蚀刻停止层的高应力层，以增强场效应晶体管的相邻沟道区域中的应变产生。 此外，应变半导体材料可以通过减少或避免金属硅化物的不适当的松弛效应来定位在靠近沟道区域，从而也为应变产生提供增强的效率。 在一些方面，两种效应可以组合以获得更有效的应变诱导机制。

公开(公告)号：US20090236667A1

公开(公告)日：2009-09-24

申请号：US12419500

申请日：2009-04-07

Applicant: Christoph Schwan ,  Joe Bloomquist ,  Peter Javorka ,  Manfred Horstmann ,  Sven Beyer ,  Markus Forsberg ,  Frank Wirbeleit ,  Karla Romero

Inventor： Christoph Schwan ,  Joe Bloomquist ,  Peter Javorka ,  Manfred Horstmann ,  Sven Beyer ,  Markus Forsberg ,  Frank Wirbeleit ,  Karla Romero

IPC: H01L27/088

CPC classification number: H01L21/823878 ,  H01L21/76229 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846

Abstract: By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.

Abstract translation: 通过基于分离的工艺顺序形成不同类型的固有应力的隔离沟槽，可以调节相邻有源半导体区域的应变特性以获得整体器件性能。 例如，可以在相应的隔离沟槽中适当地提供包括压缩和拉伸应力的高应力电介质填充材料，以便相应地适应各个沟道区的电荷载流子迁移率。

公开(公告)号：US07547610B2

公开(公告)日：2009-06-16

申请号：US11734320

申请日：2007-04-12

Applicant: Christoph Schwan ,  Joe Bloomquist ,  Peter Javorka ,  Manfred Horstmann ,  Sven Beyer ,  Markus Forsberg ,  Frank Wirbeleit ,  Karla Romero

Inventor： Christoph Schwan ,  Joe Bloomquist ,  Peter Javorka ,  Manfred Horstmann ,  Sven Beyer ,  Markus Forsberg ,  Frank Wirbeleit ,  Karla Romero

IPC: H01L21/76

CPC classification number: H01L21/823878 ,  H01L21/76229 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846

Abstract: By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.

Abstract translation: 通过基于分离的工艺顺序形成不同类型的固有应力的隔离沟槽，可以调节相邻有源半导体区域的应变特性以获得整体器件性能。 例如，可以在相应的隔离沟槽中适当地提供包括压缩和拉伸应力的高应力电介质填充材料，以便相应地适应各个沟道区的电荷载流子迁移率。

公开(公告)号：US20080079085A1

公开(公告)日：2008-04-03

申请号：US11734320

申请日：2007-04-12

Applicant: Christoph Schwan ,  Joe Bloomquist ,  Peter Javorka ,  Manfred Horstmann ,  Sven Beyer ,  Markus Forsberg ,  Frank Wirbeleit ,  Karla Romero

Inventor： Christoph Schwan ,  Joe Bloomquist ,  Peter Javorka ,  Manfred Horstmann ,  Sven Beyer ,  Markus Forsberg ,  Frank Wirbeleit ,  Karla Romero

IPC: H01L21/762 ,  H01L23/58 ,  H01L29/78

CPC classification number: H01L21/823878 ,  H01L21/76229 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846

Abstract: By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.

Abstract translation: 通过基于分离的工艺顺序形成不同类型的固有应力的隔离沟槽，可以调节相邻有源半导体区域的应变特性以获得整体器件性能。 例如，可以在相应的隔离沟槽中适当地提供包括压缩和拉伸应力的高应力电介质填充材料，以便相应地适应各个沟道区的电荷载流子迁移率。

公开(公告)号：US20070252205A1

公开(公告)日：2007-11-01

申请号：US11609995

申请日：2006-12-13

Applicant: Jan Hoentschel ,  Andy Wei ,  Joe Bloomquist ,  Manfred Horstmann

Inventor： Jan Hoentschel ,  Andy Wei ,  Joe Bloomquist ,  Manfred Horstmann

IPC: H01L27/12 ,  H01L21/336

CPC classification number: H01L29/78609 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78621

Abstract: By introducing a atomic species, such as carbon, fluorine and the like, into the drain and source regions, as well as in the body region, the junction leakage of SOI transistors may be significantly increased, thereby providing an enhanced leakage path for accumulated minority charge carriers. Consequently, fluctuations of the body potential may be significantly reduced, thereby improving the overall performance of advanced SOI devices. In particular embodiments, the mechanism may be selectively applied to threshold voltage sensitive device areas, such as static RAM areas.

Abstract translation: 通过将诸如碳，氟等的原子物质引入漏极和源极区域以及在体区域中，可以显着增加SOI晶体管的结漏电，从而为累积的少数族群提供增强的泄漏路径 电荷载体。 因此，体电位的波动可能会显着降低，从而提高先进的SOI器件的整体性能。 在特定实施例中，可以将机构选择性地应用于阈值电压敏感设备区域，例如静态RAM区域。