摘要:
A signal processing system includes a digital sample rate converter to convert a signal sampled at a first sampling frequency into a corresponding signal sampled at a second sampling frequency. In at least one embodiment, the sample rate converter includes a digital sample rate conversion filter. The digital sample rate conversion filter includes a digital filter that models a continuous time filter such as a low pass RC filter and generates filtered samples. The digital sample rate conversion filter also includes an interpolation filter that determines samples between the digital filtered samples. A sample selector selects the samples generated by the interpolation filter at the second sampling frequency. In at least one embodiment, the sample selector determines when to generate interpolated samples and the amount of time offset from an adjacent sample generated by the digital filter.
摘要:
A personal audio device, such as a wireless telephone, includes noise canceling circuit that adaptively generates an anti-noise signal from a reference microphone signal and injects the anti-noise signal into the speaker or other transducer output to cause cancellation of ambient audio sounds. An error microphone may also be provided proximate the speaker to measure the output of the transducer in order to control the adaptation of the anti-noise signal and to estimate an electro-acoustical path from the noise canceling circuit through the transducer. A processing circuit that performs the adaptive noise canceling (ANC) function also either adjusts the frequency response of the anti-noise signal with respect to the reference microphone signal, and/or by adjusting the response of the adaptive filter independent of the adaptation provided by the reference microphone signal.
摘要:
An electronic system includes a low breakdown voltage (LBV) switch internal to an integrated circuit controller to control conductivity of an external, high breakdown voltage (HBV) switch. In at least one embodiment, the internal LBV switch and a cascode configuration of the LBV and HBV switches allow the controller to control the LBV switch and the HBV switch using an internal (“on-chip”) control signal. In at least one embodiment, the LBV switch and the cascode configuration of the HBV switch also allows the controller to control the LBV and HBV switches with more accuracy and less parasitic losses relative to directly controlling the HBV switch. Thus, in at least one embodiment, the low breakdown voltage switch is fabricated as part of an integrated circuit controller, and the high breakdown voltage switch is fabricated separately and located external to the integrated circuit controller.
摘要:
A signal processing system includes a level dependent bass management system. The level dependent bass management system utilizes audio input signal level information to apply at least one of multiple, available bass management solutions to generate one or more output signals from the audio input signal. In at least one embodiment, initially the level dependent bass management system boosts components of the audio input signal in the low frequency range by an amount sufficient to at least partially compensate for low frequency attenuation of the first speaker without exceeding one or more acceptable limitations of the signal processing system. If boosting alone cannot completely compensate for low frequency attenuation of the first speaker without exceeding one or more acceptable limitations of the signal processing system, the level dependent bass management system processes the audio input signal using an alternate low frequency management solution.
摘要:
A cascaded power converter having an auxiliary power supply operated from the second switching power stage provides efficient operation by activating the auxiliary power supply early in the startup process. A low energy transfer operating mode is initiated in the second switching power stage to charge the auxiliary power supply output without generating significant disruption at the load. After the first switching power stage is started and the intermediate node voltage has increased to a level sufficient to operate the second switching power stage, the final switching power stage enters a normal operating mode. The low energy transfer operating mode has a substantially reduced switching rate and pulse width from that of the normal operating mode.
摘要:
A discrete time delta-sigma modulator circuit, which may be used to implement an analog-to-digital converter (ADC) provides improved anti-aliasing performance when lower quantization rates are selected, by maintaining the clocking rate of a first stage in the delta-sigma modulator loop filter at a rate higher than would ordinarily be selected for a lower quantization rate. To accomplish the anti-aliasing improvement, the ratio between the quantization rate and the clocking rate of the first integrator is reduced at the lower quantization rate, resulting in a first true alias image at a multiple of the quantization rate, permitting anti-aliasing filters to more effectively attenuate the alias image, and attenuating the images spaced at the quantization rate via the averaging operation of the first integrator.
摘要:
A power control system includes a switch mode controller to control the switching mode of a switching power converter. The switch mode controller generates a switch control signal that controls conductivity of a switch of the switching power converter. Controlling conductivity of the switch controls the switch mode of the switching power converter. The switch mode controller includes a period generator to determine a period of the switch control signal and to vary the determined period to generate a broad frequency spectrum of the switch control signal when the determined period corresponds with a frequency in at least a portion of an audible frequency band. Generating a switch control signal with a broad frequency spectrum in the audible frequency band allows the system to utilize switching frequencies in the audible frequency band.
摘要:
A delta-sigma analog-to-digital converter (ADC) circuit improves performance by reducing the amount of noise and other error sampled by the reference switching circuit. The reference is operated such that one or more reference capacitors remain coupled to an input summing node of the ADC input integrator when an input value to a feedback digital-to-analog converter (DAC) indicates that their contribution is not required to apply a reference in the next quantization period. The reference switching network can select from two or more of the following reference options: 1) switch the reference capacitor to apply a charge quanta as per an ordinary switched-capacitor cycle, 2) switch the reference voltage on a second terminal of the reference capacitor to apply an opposite polarity charge quanta, or 3) leave the first terminal of the reference capacitor coupled to the integrator without changing the voltage at the second terminal of the reference capacitor.
摘要:
A power control system includes a switching power converter and a programmable power factor correction (PFC) and output voltage controller. The programmable PFC and output voltage controller generates a control signal to control power factor correction and voltage regulation of the switching power converter. In at least one embodiment, the control signal is a pulse width modulated signal. The programmability of the PFC and output voltage controller provides the programmable PFC and output voltage controller flexibility to operate in accordance with programmable parameters, to adapt to various operating environments, and to respond to various operating exigencies. In at least one embodiment, the programmable PFC and output voltage controller includes a state machine to process one or more programmable, operational parameters to determine the period and pulse width states of the control signal.
摘要:
A power control system includes a switching power converter and a controller, and the controller responds to a time-varying voltage source signal by generating a switch control signal having a period that varies in accordance with at least one of the following: (i) the period of the switch control signal trends inversely to estimated power delivered to a load coupled to the switching power converter, (ii) the period of the switch control signal trends inversely to instantaneous voltage levels of the voltage source signal, and (iii) the period of the switch control signal trends directly with a line voltage level of the time-varying voltage source signal. In at least one embodiment, the controller achieves an efficient correlation between the switching period with associated switching losses and the instantaneous power transferred to the switching power converter while providing power factor correction (PFC).