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1.发明授权Method and apparatus for controlling a selectable voltage audio power output stage 有权用于控制可选择的电压音频功率输出级的方法和装置公开(公告)号：US08068622B2
公开(公告)日：2011-11-29
申请号：US11611069
申请日：2006-12-14
IPC分类号： H03F99/00
CPC分类号： H03F1/025
摘要： A method and apparatus for controlling a selectable voltage audio power output stage provides a mechanism for raising the selected power amplifier output voltage in time for the arrival of signal peaks to avoid clipping. Signal peaks may either be delayed by delaying an increase in volume control level or enabling signal compression for a predetermined time period, so that sufficient time is provided for the amplifier power supply to stabilize at a higher operating voltage when an increase of power supply voltage is selected. Alternatively, a signal level may be determined at an upstream source, such as a decoder or filter that provides information in sufficient advance of the arrival of the peaks, and used to control the power supply selection, so that the higher power supply voltage level is selected in advance of arrival of the signal peaks that would otherwise cause clipping at the power amplifier output.
摘要翻译： 用于控制可选择的电压音频功率输出级的方法和装置提供了用于在信号峰值到达时及时提升所选择的功率放大器输出电压以避免削波的机制。 信号峰值可以通过延迟音量控制电平的增加或在预定时间段内启用信号压缩来延迟，使得当电源电压的增加是放大器电源稳定在较高的工作电压时，提供足够的时间 选择。 或者，可以在诸如解码器或滤波器的上游源处确定信号电平，所述解码器或滤波器提供足够高的峰值到达之前的信息，并且用于控制电源选择，使得较高的电源电压电平为 在信号峰值的到达之前选择，否则将在功率放大器输出端造成限幅。
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公开(公告)号：US20080044041A1
公开(公告)日：2008-02-21
申请号：US11610496
申请日：2006-12-13
IPC分类号： H03F21/00
CPC分类号： H03G3/004 , H02M3/07 , H03F1/0227 , H03F1/025 , H03F3/183 , H03F2200/03 , H03F2200/211 , H03F2200/507 , H03G3/20 , H03G3/3031
摘要： An energy-efficient consumer device audio power output stage provides improved battery life and reduced power dissipation. A power supply having a selectable operating mode supplies the power supply rails to the power amplified output stage. The operating mode is controlled in conformity with the audio signal level, which may be determined from a volume control setting of the device and/or from a signal level detector that determines the amplitude of the signal being amplified. The power supply may be a charge pump in which the operating mode uses a capacitive divider to provide for selection of a power supply output voltage that is a rational fraction of the power supply output voltage in a full-voltage operating mode.
摘要翻译： 节能消费者设备音频功率输出级提供更好的电池寿命和更低的功耗。 具有可选操作模式的电源将电源轨提供给功率放大输出级。 操作模式根据音频信号电平进行控制，音频信号电平可以根据设备的音量控制设置和/或从确定被放大的信号的幅度的信号电平检测器确定。 电源可以是电荷泵，其中操作模式使用电容分压器来提供在全电压工作模式下选择作为电源输出电压的有效部分的电源输出电压。
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公开(公告)号：US20140050330A1
公开(公告)日：2014-02-20
申请号：US13588021
申请日：2012-08-17
IPC分类号： H04R1/10
CPC分类号： H04R3/00 , H04R5/033 , H04R5/04 , H04R29/00 , H04R2420/05
摘要： A circuit including headset type detection provides compatibility with different transducer types, such as headphones provided by different manufacturers. An audio circuit that generates or receives an audio signal includes electrical terminals for coupling to a transducer device, at least one of which carries the audio signal. A transducer device type detection circuit is included and detects a type of a transducer device coupled to the audio device from characteristics measured at the multiple electrical terminals when the transducer is coupled to the audio device. The circuit also includes a configuration control circuit for altering a configuration of the audio device according to a detected type of the transducer device.
摘要翻译： 包括耳机类型检测的电路提供与不同传感器类型的兼容性，例如由不同制造商提供的耳机。 产生或接收音频信号的音频电路包括用于耦合到换能器装置的电端子，其中至少一个承载音频信号。 包括传感器装置类型检测电路，并且当换能器耦合到音频装置时，根据在多个电端子处测量的特性来检测耦合到音频装置的换能器装置的类型。 电路还包括配置控制电路，用于根据检测到的换能器装置的类型改变音频装置的配置。
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4.发明授权Audio processor with internal oscillator-generated audio intermediate frequency reference 有权具有内部振荡器产生音频中频参考的音频处理器公开(公告)号：US08452429B2
公开(公告)日：2013-05-28
申请号：US12412936
申请日：2009-03-27
IPC分类号： G06F17/00
CPC分类号： G06F17/00 , H03H17/0628 , H03L1/02
摘要： An integrated circuit audio processor having an internal-oscillator generated intermediate frequency reference provides for operation of an audio processor without requiring an external master clock. Input audio streams are sample-rate converted to an intermediate sample rate derived from the internal oscillator, which may be an LC oscillator. One or more output audio streams are generated from the one or more input audio streams at the intermediate sample rate and are converted from the intermediate sample rate to corresponding output sample rates. A divider generates the intermediate sample rate from the oscillator output, and is programmed to control the intermediate sample rate to ensure that the intermediate sample rate is in the proper range for operation of the integrated circuit. The divider can be programmed to accommodate changes in process, voltage and/or temperature of the IC, so that the intermediate sample rate is maintained near an expected frequency.
摘要翻译： 具有内部振荡器产生的中频参考的集成电路音频处理器提供音频处理器的操作而不需要外部主时钟。 输入音频流被采样率转换成从内部振荡器得到的中间采样速率，内部振荡器可以是LC振荡器。 从中间采样率的一个或多个输入音频流产生一个或多个输出音频流，并从中间采样率转换为对应的输出采样率。 分压器从振荡器输出产生中间采样率，并且被编程为控制中间采样率，以确保中间采样率在集成电路的操作的适当范围内。 分频器可以被编程以适应IC的过程，电压和/或温度的变化，使得中间采样率保持在预期频率附近。
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5.发明授权Modulated gain audio control and zipper noise suppression techniques using modulated gain 有权使用调制增益的调制增益音频控制和拉链噪声抑制技术公开(公告)号：US08249275B1
公开(公告)日：2012-08-21
申请号：US12493054
申请日：2009-06-26
IPC分类号： H04B15/00
CPC分类号： H03F1/305 , H03F3/189 , H03F3/45475 , H03F2200/171 , H03F2203/45522 , H03G1/0088
摘要： A modulated gain audio control and zipper noise suppression techniques provide reduction in audible artifacts caused by discrete-valued gain changes. The gain of a signal is controlled by modulating between multiple gain values for corresponding time durations, so that a resulting average gain is controlled according to the average of the multiple gain values as weighted by their corresponding time durations. The modulation frequency is above the bandwidth of the signal. Transitions between gain levels are performed by changing the relative proportion of the durations to slowly change the gain according to a transition profile, which may be linear or non-linear. The modulation employed may be pulse-width modulation, or another modulation pattern such as a delta-sigma modulation pattern.
摘要翻译： 调制增益音频控制和拉链噪声抑制技术提供了由离散值增益变化引起的声音伪像的减少。 通过在相应的持续时间的多个增益值之间进行调制来控制信号的增益，从而根据由相应的持续时间加权的多个增益值的平均值来控制所得到的平均增益。 调制频率高于信号的带宽。 通过改变持续时间的相对比例来实现增益水平之间的转换，以根据可以是线性或非线性的转移轮廓来缓慢地改变增益。 所采用的调制可以是脉冲宽度调制，或者诸如Δ-Σ调制模式的另一种调制模式。
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6.发明授权Discrete-time delta-sigma modulator with improved anti-aliasing at lower quantization rates 有权离散时间Δ-Σ调制器，在较低量化速率下具有改进的抗锯齿公开(公告)号：US08130127B1
公开(公告)日：2012-03-06
申请号：US12827522
申请日：2010-06-30
IPC分类号： H03M3/00
摘要： A discrete time delta-sigma modulator circuit, which may be used to implement an analog-to-digital converter (ADC) provides improved anti-aliasing performance when lower quantization rates are selected, by maintaining the clocking rate of a first stage in the delta-sigma modulator loop filter at a rate higher than would ordinarily be selected for a lower quantization rate. To accomplish the anti-aliasing improvement, the ratio between the quantization rate and the clocking rate of the first integrator is reduced at the lower quantization rate, resulting in a first true alias image at a multiple of the quantization rate, permitting anti-aliasing filters to more effectively attenuate the alias image, and attenuating the images spaced at the quantization rate via the averaging operation of the first integrator.
摘要翻译： 可用于实现模数转换器（ADC）的离散时间Δ-Σ调制器电路通过将第一级的时钟速率保持在三角形（delta）中来提供较低量化速率时提供的改进的抗混叠性能 Σ调制器环路滤波器的速率高于通常为较低量化速率选择的速率。 为了实现抗锯齿改进，第一积分器的量化速率与时钟速率之间的比例以较低的量化速率降低，从而产生了以量化速率倍数的第一真实混叠图像，从而允许抗混叠滤波器 以更有效地衰减别名图像，并且通过第一积分器的平均化操作来衰减以量化速率间隔的图像。
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7.发明申请METHOD AND APPARATUS FOR CONTROLLING A SELECTABLE VOLTAGE AUDIO POWER OUTPUT STAGE 有权用于控制可选择的电压音频功率输出级的方法和装置公开(公告)号：US20080144861A1
公开(公告)日：2008-06-19
申请号：US11611069
申请日：2006-12-14
IPC分类号： H03F21/00
CPC分类号： H03F1/025
摘要： A method and apparatus for controlling a selectable voltage audio power output stage provides a mechanism for raising the selected power amplifier output voltage in time for the arrival of signal peaks to avoid clipping. Signal peaks may either be delayed by delaying an increase in volume control level or enabling signal compression for a predetermined time period, so that sufficient time is provided for the amplifier power supply to stabilize at a higher operating voltage when an increase of power supply voltage is selected. Alternatively, a signal level may be determined at an upstream source, such as a decoder or filter that provides information in sufficient advance of the arrival of the peaks, and used to control the power supply selection, so that the higher power supply voltage level is selected in advance of arrival of the signal peaks that would otherwise cause clipping at the power amplifier output.
摘要翻译： 用于控制可选择的电压音频功率输出级的方法和装置提供了用于在信号峰值到达时及时提升所选择的功率放大器输出电压以避免削波的机制。 信号峰值可以通过延迟音量控制电平的增加或在预定时间段内启用信号压缩来延迟，使得当电源电压的增加是放大器电源稳定在较高的工作电压时，提供足够的时间 选择。 或者，可以在诸如解码器或滤波器的上游源处确定信号电平，所述解码器或滤波器提供足够高的峰值到达之前的信息，并且用于控制电源选择，使得较高的电源电压电平为 在信号峰值的到达之前选择，否则将在功率放大器输出端造成限幅。
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8.发明授权Method and system for operating two or more integrators with different power supplies for an analog-to-digital delta-sigma modulator 有权用于操作具有不同电源的两个或更多个积分器用于模数转换Δ-Σ调制器的方法和系统公开(公告)号：US06400297B1
公开(公告)日：2002-06-04
申请号：US09843393
申请日：2001-04-26
IPC分类号： H03M300
摘要： A method and system are disclosed for operating two or more integrator amplifiers with different power supplies for a modulator of an analog-to-digital (“A/D”) converter. A first, upstream integrator is operated with one power supply, and the other downstream integrator(s) is/are operated with at least another power supply. The modulator has amplifiers with coefficient gains having values that are determined and set so that voltage levels for the at least another integrator are maintained within operating and output limits. An integrating coefficient gain k1 for the first integrator is set to have a sufficiently large value so that an integrating capacitor can be made small for the one integrator. Another integrating coefficient gain k2 for a second integrator is set to have a sufficiently small value so that an output voltage from the first integrator is sufficiently attenuated to a voltage value within an operating range of the second integrator.
摘要翻译： 公开了一种用于对模数（A / D）转换器的调制器运行具有不同电源的两个或多个积分放大器的方法和系统。 第一个上游集成器使用一个电源运行，另一个下游积分器至少与另一个电源一起运行。 调制器具有放大器，其系数增益具有确定和设置的值，使得至少另一个积分器的电压电平保持在操作和输出限制内。 将第一积分器的积分系数增益k1设定为具有足够大的值，使得对于一个积分器可以使积分电容器较小。 将第二积分器的另一积分系数增益k2设定为具有足够小的值，使得来自第一积分器的输出电压充分衰减到第二积分器的工作范围内的电压值。
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9.发明申请AUDIO PROCESSOR WITH INTERNAL OSCILLATOR-GENERATED AUDIO INTERMEDIATE FREQUENCY REFERENCE 有权具有内部振荡器产生的音频中频参考的音频处理器公开(公告)号：US20100182062A1
公开(公告)日：2010-07-22
申请号：US12412936
申请日：2009-03-27
IPC分类号： H03L7/00
CPC分类号： G06F17/00 , H03H17/0628 , H03L1/02
摘要： An integrated circuit audio processor having an internal-oscillator generated intermediate frequency reference provides for operation of an audio processor without requiring an external master clock. Input audio streams are sample-rate converted to an intermediate sample rate derived from the internal oscillator, which may be an LC oscillator. One or more output audio streams are generated from the one or more input audio streams at the intermediate sample rate and are converted from the intermediate sample rate to corresponding output sample rates. A divider generates the intermediate sample rate from the oscillator output, and is programmed to control the intermediate sample rate to ensure that the intermediate sample rate is in the proper range for operation of the integrated circuit. The divider can be programmed to accommodate changes in process, voltage and/or temperature of the IC, so that the intermediate sample rate is maintained near an expected frequency.
摘要翻译： 具有内部振荡器产生的中频参考的集成电路音频处理器提供音频处理器的操作而不需要外部主时钟。 输入音频流被采样率转换成从内部振荡器得到的中间采样速率，内部振荡器可以是LC振荡器。 从中间采样率的一个或多个输入音频流产生一个或多个输出音频流，并从中间采样率转换为对应的输出采样率。 分压器从振荡器输出产生中间采样率，并且被编程为控制中间采样率，以确保中间采样率在集成电路的操作的适当范围内。 分频器可以被编程以适应IC的过程，电压和/或温度的变化，使得中间采样率保持在预期频率附近。
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公开(公告)号：US07170338B1
公开(公告)日：2007-01-30
申请号：US11088654
申请日：2005-03-24
IPC分类号： H03F1/02
CPC分类号： H03F3/45775 , H03F3/2178 , H03F3/393 , H03F3/45192 , H03F3/45475 , H03F2200/03 , H03F2200/372 , H03F2203/45138 , H03F2203/45212 , H03F2203/45292 , H03F2203/45302 , H03F2203/45356 , H03F2203/45396
摘要： An amplifier including a current source transistor for supplying a current to a node from a voltage rail and an input transistor switching the current at the node in response to an input signal chopped by a chopping signal. A cascode-chopping transistor operating both as a cascode transistor and a chopping transistor couples the node and an amplifier output in response to a bias voltage chopped by the chopping signal.
摘要翻译： 一种放大器，包括：电流源晶体管，用于从电压轨提供电流到节点;以及输入晶体管，响应于由斩波信号斩波的输入信号切换所述节点处的电流。 作为共源共栅晶体管和斩波晶体管的共源共栅斩波晶体管响应于由斩波信号斩波的偏置电压而耦合节点和放大器输出。
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