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公开(公告)号：US12021541B2
公开(公告)日：2024-06-25
申请号：US18129527
申请日：2023-03-31
Applicant: SIGMASENSE, LLC.
Inventor： Phuong Huynh
CPC classification number: H03M1/004 , H03M1/0626 , H03M1/0854 , H03M1/1245 , H03M1/34 , H03M3/462 , H03M3/476 , H03M3/422
Abstract: A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.
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2.发明申请CAPACITANCE-TO-DIGITAL CONVERTER UTILIZING DIGITAL FEEDBACK AND AUXILIARY DAC 有权使用数字反馈和辅助DAC的电容数字转换器公开(公告)号：US20160182081A1
公开(公告)日：2016-06-23
申请号：US14575167
申请日：2014-12-18
Applicant: Silicon Laboratories Inc.
Inventor： Michael H. Perrott , Louis Nervegna
IPC: H03M3/00
CPC classification number: H03M3/362 , G01D5/24 , G01N27/26 , G01R17/105 , G01R27/2605 , H03M3/464 , H03M3/476 , H03M3/496 , Y10T307/729
Abstract: A capacitance-to-digital converter circuit s a capacitor bridge circuit to sense a difference in capacitance between sense capacitors and fixed capacitors in the bridge circuit. The sense capacitors vary according to a sensed parameter. Auxiliary capacitor digital to analog converters (DACs) are coupled to the capacitor bridge circuit to cancel the sensed difference. An analog to digital converter (ADC) receives a signal generated by the capacitor bridge circuit and the auxiliary capacitor DACs and converts the received signal to a digital signal. A digital accumulator accumulates the ADC output, whose output represents the difference in capacitance between the sense capacitors and the fixed capacitors. The accumulator output is used to control the auxiliary capacitor DACs to offset the difference in capacitance between the sense capacitors and the fixed capacitors. The accumulator output also provides the basis for the capacitance-to-digital circuit output.
Abstract translation: 电容 - 数字转换器电路是用于感测桥式电路中的感测电容器和固定电容器之间的电容差的电容器桥接电路。 感测电容器根据感测参数而变化。 辅助电容器数模转换器（DAC）耦合到电容器桥接电路以消除感测到的差异。 模数转换器（ADC）接收由电容器桥电路和辅助电容DAC产生的信号，并将接收的信号转换为数字信号。 数字累加器累加ADC输出，其输出表示感测电容器和固定电容器之间的电容差。 累加器输出用于控制辅助电容DAC以抵消感测电容器和固定电容器之间的电容差。 累加器输出也为电容 - 数字电路输出提供了基础。
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3.发明授权Sigma-delta difference-of-squares log-RMS to DC converter with forward path multiplier and chopper stabilization 有权具有正向路径乘法器和斩波稳定的Sigma-delta平方和对数RMS到DC转换器公开(公告)号：US08665128B2
公开(公告)日：2014-03-04
申请号：US12963265
申请日：2010-12-08
IPC: H03M3/00
Abstract: A sigma-delta (ΣΔ) difference-of-squares LOG-RMS to digital converter for true RMS detection by merging a ΣΔ modulator with an analog LOG-RMS to DC converter based on a difference-of-squares. Chopper-stabilization, implemented through commutators running at two different frequencies, can be employed to reduce sensitivity to DC offsets and low-frequency errors, resulting in an extension of the useful input-referred dynamic range. High-order ΣΔ LOG-RMS converters can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The resulting implementations are ΣΔ difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range.
Abstract translation: 通过将SigmaDelta调制器与基于平方差的模拟LOG-RMS到DC转换器合并，将Σ-Δ（SigmaDelta）的差分均值LOG-RMS数字转换器用于真有效值检测。 可以采用通过以两种不同频率运行的换向器实现的斩波稳定，以降低对直流偏移和低频误差的灵敏度，从而导致有用的输入参考动态范围的扩展。 高阶SigmaDelta LOG-RMS转换器可以使用包含多个积分器的环路滤波器和用于频率补偿的前馈和/或反馈路径来实现。 所得到的实现是具有自然数字输出和对数压缩动态范围的SigmaDelta差分方差LOG-RMS到DC转换器。
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4.发明申请SIGMA-DELTA DIFFERENCE-OF-SQUARES LOG-RMS TO DC CONVERTER WITH FORWARD AND FEEDBACK PATHS SIGNAL SQUARING 有权SIGMA-DELTA差分差分直流转换器，带前馈和反馈信号平方公开(公告)号：US20120146824A1
公开(公告)日：2012-06-14
申请号：US12963198
申请日：2010-12-08
IPC: H03M3/00
Abstract: A sigma-delta (ΣΔ) difference-of-squares LOG-RMS to digital converter” by merging a traditional ΣΔ modulator with an analog LOG-RMS to DC converter based on a difference-of-squares concept. Two basic architectures include one based on two squaring cells in the feedforward and feedback paths and a second based on a single squaring cell in the forward path. High-order ΣΔ LOG-RMS can be implemented with a loop filter containing multiple integrators and feedforward and/or feedback paths for frequency compensation. The embodiments as described allow the implementations of ΣΔ difference-of-squares LOG-RMS to DC converters with a natural digital output and a logarithmically compressed dynamic range.
Abstract translation: 通过合并传统的＆Sgr＆Dgr，将Σ-Δ（＆Sgr＆amp; Dgr）的平方差LOG-RMS转换为数字转换器“ 基于平方差概念的具有模拟LOG-RMS到DC转换器的调制器。 两个基本架构包括基于前馈和反馈路径中的两个平方单元的基础架构，另一个基于前向路径中的单个正方形单元。 高等学校 LOG-RMS可以用包含多个积分器的环路滤波器和用于频率补偿的前馈和/或反馈路径来实现。 所描述的实施例允许实现＆Sgr;＆Dgr; 具有自然数字输出和对数压缩的动态范围的方差的LOG-RMS到DC转换器。
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公开(公告)号：US07888922B2
公开(公告)日：2011-02-15
申请号：US11967272
申请日：2007-12-31
Applicant: John L. Melanson
Inventor： John L. Melanson
CPC classification number: H02M1/4225 , H03M3/476 , Y02B70/126 , Y02P80/112
Abstract: A power control system includes a switching power converter and a power factor correction (PFC) and output voltage controller. The PFC and output voltage controller provides a control signal to a switch to control power factor correction and regulate output voltage of the switching power converter. During a single period of the control signal, the PFC and output voltage controller determines the line input voltage, the output voltage, or both using a single feedback signal received from the switching power converter. The feedback signal is received from a switch node located between an inductor and the switch. The PFC and output voltage controller determines either the line input voltage or the output voltage, whichever was not determined from the feedback signal, using a second feedback signal received from either a PFC stage or a driver stage of the switching power converter.
Abstract translation: 功率控制系统包括开关功率转换器和功率因数校正（PFC）和输出电压控制器。 PFC和输出电压控制器为开关提供控制信号，以控制功率因数校正并调节开关电源转换器的输出电压。 在控制信号的单个周期期间，PFC和输出电压控制器使用从开关功率转换器接收的单个反馈信号来确定线路输入电压，输出电压或两者。 反馈信号从位于电感器和开关之间的开关节点接收。 使用从PFC级或开关功率转换器的驱动级接收的第二反馈信号，PFC和输出电压控制器确定线路输入电压或输出电压（取决于未从反馈信号确定）。
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Patent Agency Ranking
公开(公告)号：US20080272746A1
公开(公告)日：2008-11-06
申请号：US11967272
申请日：2007-12-31
Applicant: John L. Melanson
Inventor： John L. Melanson
CPC classification number: H02M1/4225 , H03M3/476 , Y02B70/126 , Y02P80/112
Abstract: A power control system includes a switching power converter and a power factor correction (PFC) and output voltage controller. The PFC and output voltage controller provides a control signal to a switch to control power factor correction and regulate output voltage of the switching power converter. During a single period of the control signal, the PFC and output voltage controller determines the line input voltage, the output voltage, or both using a single feedback signal received from the switching power converter. The feedback signal is received from a switch node located between an inductor and the switch. The PFC and output voltage controller determines either the line input voltage or the output voltage, whichever was not determined from the feedback signal, using a second feedback signal received from either a PFC stage or a driver stage of the switching power converter.
Abstract translation: 功率控制系统包括开关功率转换器和功率因数校正（PFC）和输出电压控制器。 PFC和输出电压控制器为开关提供控制信号，以控制功率因数校正并调节开关电源转换器的输出电压。 在控制信号的单个周期期间，PFC和输出电压控制器使用从开关功率转换器接收的单个反馈信号来确定线路输入电压，输出电压或两者。 反馈信号从位于电感器和开关之间的开关节点接收。 使用从PFC级或开关功率转换器的驱动级接收的第二反馈信号，PFC和输出电压控制器确定线路输入电压或输出电压（取决于未从反馈信号确定）。
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7.发明申请Transmitter having a sigma-delta modulator with a non-uniform polar quantizer and methods thereof 审中-公开具有具有非均匀极化量化器的Σ-Δ调制器的发射器及其方法公开(公告)号：US20030123566A1
公开(公告)日：2003-07-03
申请号：US10026662
申请日：2001-12-27
Inventor： Jaime Hasson
IPC: H04L027/10
CPC classification number: H03M3/476 , H03M3/40 , H03M3/456 , H04L27/2057
Abstract: In some embodiments of the present invention, a transmitter includes a switching amplifier and a sigma-delta N-PSK modulator. The sigma-delta N-PSK modulator includes a non-uniform polar quantizer.
Abstract translation: 在本发明的一些实施例中，发射机包括开关放大器和Σ-ΔN-PSK调制器。 Σ-ΔN-PSK调制器包括非均匀的极化量化器。
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公开(公告)号：US12021540B2
公开(公告)日：2024-06-25
申请号：US18127400
申请日：2023-03-28
Applicant: SIGMASENSE, LLC.
Inventor： Phuong Huynh
CPC classification number: H03M1/004 , H03M1/0626 , H03M1/0854 , H03M1/1245 , H03M1/34 , H03M3/462 , H03M3/476 , H03M3/422
Abstract: A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.
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公开(公告)号：US11863197B2
公开(公告)日：2024-01-02
申请号：US18092959
申请日：2023-01-04
Applicant: SigmaSense, LLC.
Inventor： Phuong Huynh
CPC classification number: H03M1/0626 , H03M1/1245 , H03M1/462 , H03M1/464 , H03M1/84 , H03M3/32 , H03M3/43 , H03M3/462 , H03M3/476
Abstract: An analog to digital converter (ADC) senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. The digital output signal provided to the N-bit DAC is an inverse function of the load current. The ADC is operative to sense very low currents (e.g., currents as low as is of pico-amps) and consume very little power (e.g., less than 2 μW).
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公开(公告)号：US11683045B2
公开(公告)日：2023-06-20
申请号：US17876617
申请日：2022-07-29
Applicant: SIGMASENSE, LLC.
Inventor： Phuong Huynh
CPC classification number: H03M1/004 , H03M1/0626 , H03M1/0854 , H03M1/1245 , H03M1/34 , H03M3/462 , H03M3/476 , H03M3/422
Abstract: A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.
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