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    SEMICONDUCTOR DEVICE HAVING DRIVING TRANSISTORS
    11.
    发明申请
    SEMICONDUCTOR DEVICE HAVING DRIVING TRANSISTORS 有权
    具有驱动晶体管的半导体器件

    公开(公告)号：US20090294821A1

    公开(公告)日：2009-12-03

    申请号：US12473055

    申请日：2009-05-27

    申请人： Jong-In YUN ,  Soon-Moon JUNG ,  Han-Soo KIM ,  Hoo-Sung CHO ,  Jun-Beom PARK ,  Jae-Hun JEONG

    发明人： Jong-In YUN ,  Soon-Moon JUNG ,  Han-Soo KIM ,  Hoo-Sung CHO ,  Jun-Beom PARK ,  Jae-Hun JEONG

    IPC分类号： H01L29/78 ,  H01L21/762

    CPC分类号： H01L21/76224 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： One embodiment exemplarily described herein can be generally characterized as a semiconductor device that includes a lower level device layer located over a semiconductor substrate, an interlayer insulating film located over the lower level device layer and an upper level device layer located over the interlayer insulating film. The lower level device layer may include a plurality of devices formed in the substrate. The upper level device layer may include a plurality of semiconductor patterns and at least one device formed in each of the plurality of semiconductor patterns. The plurality of semiconductor patterns may be electrically isolated from each other. Each of the plurality of semiconductor patterns may include at least one active portion and at least one body contact portion electrically connected to the at least one active portion.

    摘要翻译： 本文示例性描述的一个实施方案通常可以表征为半导体器件，其包括位于半导体衬底上方的较低级器件层，位于下级器件层上的层间绝缘膜和位于层间绝缘膜上方的上位器件层。 下层器件层可以包括形成在衬底中的多个器件。 上级器件层可以包括多个半导体图案和形成在多个半导体图案中的每一个中的至少一个器件。 多个半导体图案可以彼此电隔离。 多个半导体图案中的每一个可以包括至少一个有效部分和至少一个电连接到该至少一个有效部分的主体接触部分。

    Semiconductor device and method of forming the same
    12.
    发明申请
    Semiconductor device and method of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US20090218558A1

    公开(公告)日：2009-09-03

    申请号：US12379814

    申请日：2009-03-02

    申请人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

    发明人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

    IPC分类号： H01L47/00

    CPC分类号： H01L27/24 ,  Y10S977/774

    摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.

    摘要翻译： 提供半导体器件及其形成方法。 该方法包括制备半导体衬底。 可以在半导体衬底上依次形成绝缘层。 可以在绝缘层之间形成有源元件。 可以在绝缘层中形成公共节点以电连接到有源元件。 公共节点和有源元件可以二维重复地布置在半导体衬底上。

    Semiconductor device having driving transistors
    14.
    发明授权
    Semiconductor device having driving transistors 有权
    具有驱动晶体管的半导体器件

    公开(公告)号：US08258517B2

    公开(公告)日：2012-09-04

    申请号：US12473055

    申请日：2009-05-27

    申请人： Jong-In Yun ,  Soon-Moon Jung ,  Han-Soo Kim ,  Hoo-Sung Cho ,  Jun-Beom Park ,  Jae-Hun Jeong

    发明人： Jong-In Yun ,  Soon-Moon Jung ,  Han-Soo Kim ,  Hoo-Sung Cho ,  Jun-Beom Park ,  Jae-Hun Jeong

    IPC分类号： H01L29/08

    CPC分类号： H01L21/76224 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： One embodiment exemplarily described herein can be generally characterized as a semiconductor device that includes a lower level device layer located over a semiconductor substrate, an interlayer insulating film located over the lower level device layer and an upper level device layer located over the interlayer insulating film. The lower level device layer may include a plurality of devices formed in the substrate. The upper level device layer may include a plurality of semiconductor patterns and at least one device formed in each of the plurality of semiconductor patterns. The plurality of semiconductor patterns may be electrically isolated from each other. Each of the plurality of semiconductor patterns may include at least one active portion and at least one body contact portion electrically connected to the at least one active portion.

    摘要翻译： 本文示例性描述的一个实施方案通常可以表征为半导体器件，其包括位于半导体衬底上方的较低级器件层，位于下级器件层上的层间绝缘膜和位于层间绝缘膜上方的上位器件层。 下层器件层可以包括形成在衬底中的多个器件。 上级器件层可以包括多个半导体图案和形成在多个半导体图案中的每一个中的至少一个器件。 多个半导体图案可以彼此电隔离。 多个半导体图案中的每一个可以包括至少一个有效部分和至少一个电连接到该至少一个有效部分的主体接触部分。

    Methods of fabricating semiconductor devices having insulating layers with differing compressive stresses
    16.
    发明授权
    Methods of fabricating semiconductor devices having insulating layers with differing compressive stresses 有权
    制造具有不同压缩应力的绝缘层的半导体器件的方法

    公开(公告)号：US07348231B2

    公开(公告)日：2008-03-25

    申请号：US11322440

    申请日：2005-12-30

    申请人： Hyung-Shin Kwon ,  Dong-Won Lee ,  Jun-Beom Park

    发明人： Hyung-Shin Kwon ,  Dong-Won Lee ,  Jun-Beom Park

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L21/823807

    摘要： Methods of fabricating semiconductor devices are provided. An NMOS transistor and a PMOS transistor are provided on a substrate. The NMOS transistor is positioned on an NMOS region of the substrate and the PMOS transistor is positioned on a PMOS region of the substrate. A first insulating layer is provided on the NMOS transistor. The first insulating layer has a first compressive stress. A second insulating layer is provided on the PMOS transistor. The second insulating layer has a second compressive stress and a stress relief ratio higher than a stress relief ratio of the first insulating layer. A thermal treatment process is performed on the first insulating layer and the second insulating layer such that the second compressive stress of the second insulating layer is lower than the first compressive stress of the first insulating layer. Related devices are also provided.

    摘要翻译： 提供制造半导体器件的方法。 NMOS晶体管和PMOS晶体管设置在基板上。 NMOS晶体管位于衬底的NMOS区域上，PMOS晶体管位于衬底的PMOS区域上。 第一绝缘层设置在NMOS晶体管上。 第一绝缘层具有第一压缩应力。 第二绝缘层设置在PMOS晶体管上。 第二绝缘层具有比第一绝缘层的应力消除比高的第二压缩应力和应力消除比。 在第一绝缘层和第二绝缘层上进行热处理工艺，使得第二绝缘层的第二压缩应力低于第一绝缘层的第一压缩应力。 还提供了相关设备。