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    Semiconductor device and method of forming the same
    1.
    发明申请
    Semiconductor device and method of forming the same 有权

    公开(公告)号：US20110300683A1

    公开(公告)日：2011-12-08

    申请号：US13137420

    申请日：2011-08-15

    申请人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

    发明人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

    IPC分类号： H01L45/00

    CPC分类号： H01L27/24 ,  Y10S977/774

    摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.

    Semiconductor device and method of forming the same
    2.
    发明授权
    Semiconductor device and method of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US08026504B2

    公开(公告)日：2011-09-27

    申请号：US12379814

    申请日：2009-03-02

    申请人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

    发明人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

    IPC分类号： H01L47/00

    CPC分类号： H01L27/24 ,  Y10S977/774

    摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.

    摘要翻译： 提供半导体器件及其形成方法。 该方法包括制备半导体衬底。 可以在半导体衬底上依次形成绝缘层。 可以在绝缘层之间形成有源元件。 可以在绝缘层中形成公共节点以电连接到有源元件。 公共节点和有源元件可以二维重复地布置在半导体衬底上。

    Semiconductor device and method of forming the same
    3.
    发明申请
    Semiconductor device and method of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US20090218558A1

    公开(公告)日：2009-09-03

    申请号：US12379814

    申请日：2009-03-02

    申请人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

    发明人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

    IPC分类号： H01L47/00

    CPC分类号： H01L27/24 ,  Y10S977/774

    摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.

    摘要翻译： 提供半导体器件及其形成方法。 该方法包括制备半导体衬底。 可以在半导体衬底上依次形成绝缘层。 可以在绝缘层之间形成有源元件。 可以在绝缘层中形成公共节点以电连接到有源元件。 公共节点和有源元件可以二维重复地布置在半导体衬底上。

    Semiconductor device with three-dimensional array structure
    5.
    发明授权
    Semiconductor device with three-dimensional array structure 有权
    具有三维阵列结构的半导体器件

    公开(公告)号：US07646664B2

    公开(公告)日：2010-01-12

    申请号：US11869140

    申请日：2007-10-09

    申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

    发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

    IPC分类号： G11C8/00

    CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C8/14 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11568

    摘要： A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.

    摘要翻译： 一种半导体存储器件，包括存储单元阵列，与存储单元阵列相邻的第一行解码器以及与存储单元阵列相邻的第二行解码器。 存储单元阵列可以包括在相应的第一和第二半导体层上的第一和第二存储单元块。 第一存储单元块可以包括耦合到第一半导体层上的第一行存储单元的第一字线，第二存储单元块可以包括耦合到第二半导体层上的第二行存储单元的第二字线， 并且第一字线可以在第一和第二半导体层之间。 第一行解码器可以被配置为控制第一字线，并且第二行解码器可以被配置为控制第二字线。 第一布线可以电连接第一行解码器和第一字线，并且第二布线可电连接第二行解码器和第二字线。

    SEMICONDUCTOR DEVICE WITH THREE-DIMENSIONAL ARRAY STRUCTURE
    7.
    发明申请
    SEMICONDUCTOR DEVICE WITH THREE-DIMENSIONAL ARRAY STRUCTURE 有权
    具有三维阵列结构的半导体器件

    公开(公告)号：US20080084729A1

    公开(公告)日：2008-04-10

    申请号：US11869140

    申请日：2007-10-09

    申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

    发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Young-Seop Rah ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jun-Beom Park

    IPC分类号： G11C5/06

    CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C8/14 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11568

    摘要： A semiconductor memory device including a memory cell array, a first row decoder adjacent the memory cell array, and a second row decoder adjacent the memory cell array. A memory cell array may include first and second memory cell blocks on respective first and second semiconductor layers. The first memory cell block may include a first word line coupled to a first row of memory cells on the first semiconductor layer, the second memory cell block may include a second word line coupled to a second row of memory cells on the second semiconductor layer, and the first word line may be between the first and second semiconductor layers. The first row decoder may be configured to control the first word line, and the second row decoder may be configured to control the second word line. A first wiring may electrically connect the first row decoder and the first word line, and a second wiring may electrically connect the second row decoder and the second word line.

    摘要翻译： 一种半导体存储器件，包括存储单元阵列，与存储单元阵列相邻的第一行解码器以及与存储单元阵列相邻的第二行解码器。 存储单元阵列可以包括在相应的第一和第二半导体层上的第一和第二存储单元块。 第一存储单元块可以包括耦合到第一半导体层上的第一行存储单元的第一字线，第二存储单元块可以包括耦合到第二半导体层上的第二行存储单元的第二字线， 并且第一字线可以在第一和第二半导体层之间。 第一行解码器可以被配置为控制第一字线，并且第二行解码器可以被配置为控制第二字线。 第一布线可以电连接第一行解码器和第一字线，并且第二布线可电连接第二行解码器和第二字线。

    Semiconductor device having driving transistors
    10.
    发明授权
    Semiconductor device having driving transistors 有权
    具有驱动晶体管的半导体器件

    公开(公告)号：US08258517B2

    公开(公告)日：2012-09-04

    申请号：US12473055

    申请日：2009-05-27

    申请人： Jong-In Yun ,  Soon-Moon Jung ,  Han-Soo Kim ,  Hoo-Sung Cho ,  Jun-Beom Park ,  Jae-Hun Jeong

    发明人： Jong-In Yun ,  Soon-Moon Jung ,  Han-Soo Kim ,  Hoo-Sung Cho ,  Jun-Beom Park ,  Jae-Hun Jeong

    IPC分类号： H01L29/08

    CPC分类号： H01L21/76224 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： One embodiment exemplarily described herein can be generally characterized as a semiconductor device that includes a lower level device layer located over a semiconductor substrate, an interlayer insulating film located over the lower level device layer and an upper level device layer located over the interlayer insulating film. The lower level device layer may include a plurality of devices formed in the substrate. The upper level device layer may include a plurality of semiconductor patterns and at least one device formed in each of the plurality of semiconductor patterns. The plurality of semiconductor patterns may be electrically isolated from each other. Each of the plurality of semiconductor patterns may include at least one active portion and at least one body contact portion electrically connected to the at least one active portion.

    摘要翻译： 本文示例性描述的一个实施方案通常可以表征为半导体器件，其包括位于半导体衬底上方的较低级器件层，位于下级器件层上的层间绝缘膜和位于层间绝缘膜上方的上位器件层。 下层器件层可以包括形成在衬底中的多个器件。 上级器件层可以包括多个半导体图案和形成在多个半导体图案中的每一个中的至少一个器件。 多个半导体图案可以彼此电隔离。 多个半导体图案中的每一个可以包括至少一个有效部分和至少一个电连接到该至少一个有效部分的主体接触部分。