公开(公告)号：US20060195289A1

公开(公告)日：2006-08-31

申请号：US11354125

申请日：2006-02-15

申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Yong-Gu Kang ,  Jung-Yong Choi ,  Young-Hun Seo

发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Yong-Gu Kang ,  Jung-Yong Choi ,  Young-Hun Seo

IPC分类号： G01K1/00

CPC分类号： G01K7/01

摘要： A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.

公开(公告)号：US20060164903A1

公开(公告)日：2006-07-27

申请号：US11328237

申请日：2006-01-10

申请人： Jung-Yong Choi ,  Young-Gu Kang ,  Ki-Ho Jang

发明人： Jung-Yong Choi ,  Young-Gu Kang ,  Ki-Ho Jang

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C2211/4067

摘要： A semiconductor memory device supporting a self refresh operation is disclosed and comprises an address buffer unit and an operation control unit. The address buffer unit may be enabled during the self refresh operation by a first external control signal to generate an internal address signal. The operation control unit controls the start of the self refresh operation in response to the internal address signal.

摘要翻译： 公开了一种支持自刷新操作的半导体存储器件，包括地址缓冲器单元和操作控制单元。 地址缓冲单元可以在自刷新操作期间由第一外部控制信号使能以产生内部地址信号。 操作控制单元响应于内部地址信号控制自刷新操作的开始。

公开(公告)号：US06735147B2

公开(公告)日：2004-05-11

申请号：US10318446

申请日：2002-12-13

申请人： Jung-Yong Choi ,  Young-Gu Kang

发明人： Jung-Yong Choi ,  Young-Gu Kang

IPC分类号： G11C800

CPC分类号： G11C8/12

摘要： The present invention discloses a semiconductor memory device and a method of generating a block selection signal for the semiconductor memory device. The semiconductor memory device includes 2n groups comprised of m memory cell array blocks and each of the memory cell array blocks has (2k+a) word lines. The semiconductor memory device further includes a first block selection signal generating circuit for generating first block selection signals for selecting one group of the 2n groups by decoding a n-bit row address, a second block selection signal generating circuit for generating second block selection signals for selecting one memory cell array block in every group by decoding a l-bit row address, and a third block selection signal generating circuit for generating third block selection signals for selecting one memory cell array block out of (m×2n) memory cell array blocks by receiving the first block selection signals and the second block selection signals. The semiconductor memory device having (2k+a) word lines in each memory cell array block occupies less area on a semiconductor substrate than a conventional semiconductor memory device having 2k word lines.

摘要翻译： 本发明公开了一种半导体存储器件和一种用于生成半导体存储器件的块选择信号的方法。 半导体存储器件包括由m个存储单元阵列块组成的2组，并且每个存储单元阵列块具有（2k + a）个字线。 半导体存储器件还包括第一块选择信号产生电路，用于通过解码n位行地址产生用于选择一组2组的第一块选择信号;第二块选择信号产生电路，用于产生第二块 选择信号，用于通过解码1位行地址来选择每组中的一个存储单元阵列块;以及第三块选择信号产生电路，用于产生用于从（mx2 ）中选择一个存储单元阵列块的第三块选择信号， 存储单元阵列块通过接收第一块选择信号和第二块选择信号。在每个存储单元阵列块中具有（2k + a）字线的半导体存储器件在半导体衬底上占据比常规半导体 具有2K字线的存储器件。

公开(公告)号：US07889570B2

公开(公告)日：2011-02-15

申请号：US11515799

申请日：2006-09-06

申请人： Dong-woo Lee ,  Jung-yong Choi ,  Jong-hyun Choi

发明人： Dong-woo Lee ,  Jung-yong Choi ,  Jong-hyun Choi

IPC分类号： G11C7/10

CPC分类号： G11C8/06 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/225

摘要： Provided are an input buffer of a memory device, a memory controller, and a memory system making use thereof. The input buffer of a memory device is enabled or disabled in response to a first signal showing chip selection information and a second signal showing power down information, and the input buffer is enabled only when the second signal shows a non-power down mode and the first signal shows a chip selection state. The input buffer is at least one selected from the group consisting of a row address strobe input buffer, a column address strobe input buffer, and an address input buffer.

摘要翻译： 提供了存储器件，存储器控制器和使用它的存储器系统的输入缓冲器。 响应于表示芯片选择信息的第一信号和表示掉电信息的第二信号，存储器件的输入缓冲器被使能或禁止，并且仅当第二信号显示非掉电模式时，输入缓冲器被使能，并且 第一信号显示芯片选择状态。 输入缓冲器是从由行地址选通输入缓冲器，列地址选通输入缓冲器和地址输入缓冲器组成的组中选择的至少一个。

公开(公告)号：US07701795B2

公开(公告)日：2010-04-20

申请号：US11811601

申请日：2007-06-11

申请人： Dong-Woo Lee ,  Jung-Yong Choi

发明人： Dong-Woo Lee ,  Jung-Yong Choi

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/04 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/40603 ,  G11C11/40626 ,  G11C11/4093

摘要： A semiconductor memory device includes a mode register, an additional function executer, and an additional function controller. The mode register activates an additional function control signal when a mode register set code indicates that an additional function is to be executed concurrently with a refresh operation. The additional function controller controls the additional function executer to carry out the additional function concurrently with the refresh operation when the additional function control signal is activated.

摘要翻译： 半导体存储器件包括模式寄存器，附加功能执行器和附加功能控制器。 当模式寄存器组代码指示要与刷新操作同时执行附加功能时，模式寄存器激活附加功能控制信号。 当附加功能控制信号被激活时，附加功能控制器控制附加功能执行器与刷新操作同时执行附加功能。

公开(公告)号：US20080030221A1

公开(公告)日：2008-02-07

申请号：US11723518

申请日：2007-03-20

申请人： Dong-woo Lee ,  Jung-yong Choi

发明人： Dong-woo Lee ,  Jung-yong Choi

IPC分类号： H03K19/003

CPC分类号： H04L25/0278 ,  H03K19/0005

摘要： A method of controlling On-Die Termination (ODT) resistors of memory devices sharing signal lines is provided. The ODT controlling method comprises setting an ODT control enable signal of each of the memory devices and address/command or data termination information to a mode register of the corresponding memory device, and controlling resistances of ODT resistors of the signal lines in the memory devices in response to the address/command or data termination information and termination addresses. When only one of the memory devices is activated, ODT resistors of the activated memory device are set to a first resistance. When all the memory devices are activated, ODT resistors of the memory devices are set to a second resistance.

摘要翻译： 提供了一种控制共享信号线的存储器件的片上端接（ODT）电阻的方法。 ODT控制方法包括将每个存储器件的ODT控制使能信号和地址/命令或数据终止信息设置到对应的存储器件的模式寄存器，以及控制存储器件中信号线的ODT电阻的电阻 响应地址/命令或数据终止信息和终止地址。 当只有一个存储器件被激活时，激活的存储器件的ODT电阻被设置为第一个电阻。 当所有存储器件被激活时，存储器件的ODT电阻被设置为第二电阻。

公开(公告)号：US07042800B2

公开(公告)日：2006-05-09

申请号：US10951881

申请日：2004-09-29

申请人： Young-gu Kang ,  Jong-hyun Choi ,  Woo-seop Jeong ,  Ki-ho Jang ,  Jung-yong Choi

发明人： Young-gu Kang ,  Jong-hyun Choi ,  Woo-seop Jeong ,  Ki-ho Jang ,  Jung-yong Choi

IPC分类号： G11C8/00

CPC分类号： G11C7/1045 ,  G11C29/46

摘要： A memory system, memory device, and method for setting an operating mode of a memory device include a memory cell array; row and column decoders which select a row and a column of the memory cell array, respectively, according to a multi-bit address signal; and a mode control circuit which receives at least one bit from the multi-bit address signal used in the selection of the row or the column, and which sets an operating mode of the memory device according to the at least one bit, wherein the operating mode is one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.

摘要翻译： 用于设置存储器件的操作模式的存储器系统，存储器件和方法包括存储器单元阵列; 行和列解码器，其分别根据多位地址信号选择存储单元阵列的行和列; 以及模式控制电路，其从在行或列的选择中使用的多位地址信号接收至少一个位，并且根据至少一个位设置存储器件的操作模式，其中操作 模式是突发长度模式，DLL复位模式，测试模式，CAS延迟模式和突发类型模式之一。

公开(公告)号：US07894275B2

公开(公告)日：2011-02-22

申请号：US11818165

申请日：2007-06-13

申请人： Jung-yong Choi ,  Dong-woo Lee

发明人： Jung-yong Choi ,  Dong-woo Lee

IPC分类号： G11C7/10

CPC分类号： G06F13/4217 ,  Y02D10/14 ,  Y02D10/151

摘要： A method may be provided to communicate a plurality of groups of output data bits representing a respective plurality of groups of input data bits over a data bus with each group of output data bits and each group of input data bits have an equal data width. Each of the plurality of groups of input data bits at may be received at a data register. For each group of input data bits received at the data register, if a number of data bits of the group of input data bits having a first logic level is greater than half of the data width, the group of input data bits are inverted, the inverted group of input data bits are transmitted as a respective group of output data bits in parallel over the data bus, and an inversion flag associated with the respective group of output data bits is transmitted. For each group of input data bits received at the data register, if a number of data bits of the group of input data bits having a second logic level different than the first logic level is greater than half of the data width, the group of input data bits is transmitted without inversion as a respective group of output data bits in parallel over the data bus, and a non-inversion flag associated with the respective group of output data bits is transmitted. Related systems are also discussed.

摘要翻译： 可以提供一种方法，以通过数据总线与每组输出数据位和每组输入数据位具有相等的数据宽度来传送表示相应多组输入数据位的多组输出数据位。 多个输入数据组中的每一组可以在数据寄存器处被接收。 对于在数据寄存器处接收的每组输入数据位，如果具有第一逻辑电平的输入数据位组组中的数据位的数目大于数据宽度的一半，则输入数据位组被反转， 输出数据位的反相组作为数据总线上的并行输出数据位组发送，并且发送与各组输出数据位相关联的反转标志。 对于在数据寄存器处接收的每组输入数据位，如果具有与第一逻辑电平不同的第二逻辑电平的输入数据位组组中的数据位数大于数据宽度的一半，则输入组 数据位在数据总线上并行发送而不反转为相应的输出数据位组，并且发送与各组输出数据位相关联的非反转标志。 还讨论了相关系统。

公开(公告)号：US20080162778A1

公开(公告)日：2008-07-03

申请号：US11818165

申请日：2007-06-13

申请人： Jung-yong Choi ,  Dong-woo Lee

发明人： Jung-yong Choi ,  Dong-woo Lee

IPC分类号： G06F12/00

CPC分类号： G06F13/4217 ,  Y02D10/14 ,  Y02D10/151

摘要： A method may be provided to communicate a plurality of groups of output data bits representing a respective plurality of groups of input data bits over a data bus with each group of output data bits and each group of input data bits have an equal data width. Each of the plurality of groups of input data bits at may be received at a data register. For each group of input data bits received at the data register, if a number of data bits of the group of input data bits having a first logic level is greater than half of the data width, the group of input data bits are inverted, the inverted group of input data bits are transmitted as a respective group of output data bits in parallel over the data bus, and an inversion flag associated with the respective group of output data bits is transmitted. For each group of input data bits received at the data register, if a number of data bits of the group of input data bits having a second logic level different than the first logic level is greater than half of the data width, the group of input data bits is transmitted without inversion as a respective group of output data bits in parallel over the data bus, and a non-inversion flag associated with the respective group of output data bits is transmitted. Related systems are also discussed.

摘要翻译： 可以提供一种方法，以通过数据总线与每组输出数据位和每组输入数据位具有相等的数据宽度来传送表示相应多组输入数据位的多组输出数据位。 多个输入数据组中的每一组可以在数据寄存器处被接收。 对于在数据寄存器处接收的每组输入数据位，如果具有第一逻辑电平的输入数据位组组中的数据位的数目大于数据宽度的一半，则输入数据位组被反转， 输出数据位的反相组作为数据总线上的并行输出数据位组发送，并且发送与各组输出数据位相关联的反转标志。 对于在数据寄存器处接收的每组输入数据位，如果具有与第一逻辑电平不同的第二逻辑电平的输入数据位组组中的数据位数大于数据宽度的一半，则输入组 数据位在数据总线上并行发送而不反转为相应的输出数据位组，并且发送与各组输出数据位相关联的非反转标志。 还讨论了相关系统。