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公开(公告)号：US20220173943A1
公开(公告)日：2022-06-02
申请号：US17517042
申请日：2021-11-02
申请人： Kandou Labs, S.A.
发明人： Ali Hormati , Richard Simpson
摘要： Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern.
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公开(公告)号：US20220166434A1
公开(公告)日：2022-05-26
申请号：US17666242
申请日：2022-02-07
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
IPC分类号： H03L7/08 , H03L7/087 , H03L7/099 , H04L7/033 , H04L25/14 , H04L25/02 , H04L25/40 , H04L25/493 , H03K19/21 , H03L7/089
摘要： Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.
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公开(公告)号：US20220004520A1
公开(公告)日：2022-01-06
申请号：US17347590
申请日：2021-06-15
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
摘要： Methods and systems are described for receiving an input data voltage signal at a first data decision circuit of set of pipelined data decision circuits, receiving an aggregate decision feedback equalization (DFE) correction current signal from a first analog current summation bus, the aggregate DFE correction current signal comprising a plurality of DFE tap-weighted currents from respective other data decision circuits of the set of pipelined data decision circuits, determining a data output decision value based on the received input data voltage signal and the received aggregate DFE correction current signal, and generating at least one outbound DFE tap-weighted current on at least one other analog current summation bus connected to at least one other data decision circuit of the set of pipelined data decision circuits.
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公开(公告)号：US10965290B2
公开(公告)日：2021-03-30
申请号：US16399946
申请日：2019-04-30
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
IPC分类号： H03L7/08 , H03L7/087 , H03L7/099 , H04L7/033 , H04L25/14 , H04L25/02 , H04L25/40 , H04L25/493 , H03K19/21 , H03L7/089 , H04L7/00
摘要： Methods and systems are described for generating, with a local oscillator and an adjustable phase interpolator, a data-sampling clock and a variable-phase-offset eye-measurement clock, forming a received data signal using a multi-input comparator, generating, using a data slicer and the data sampling clock, a receive sample of the received data signal, and generating, using at least one eye slicer and the variable-phase-offset eye-measurement clock, a plurality of eye characteristic measurements by adjusting a sampling threshold of the at least one eye slicer and a phase offset of the variable-phase-offset eye-measurement clock.
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公开(公告)号：US10785072B2
公开(公告)日：2020-09-22
申请号：US16261502
申请日：2019-01-29
申请人： Kandou Labs, S.A.
发明人： Ali Hormati , Richard Simpson
摘要： Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern.
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公开(公告)号：US10721106B1
公开(公告)日：2020-07-21
申请号：US16378537
申请日：2019-04-08
申请人： Kandou Labs, S.A.
发明人： Ali Hormati
IPC分类号： H04L25/03
摘要： Methods and systems are described for sampling an equalized information signal to generate a sequence of data-pattern-verified edge samples and data decisions, determining a correlation between each data-pattern-verified edge sample and a corresponding penultimate prior data decision of the data decisions, and adjusting, responsive to the correlation, a continuous-time linear equalization (CTLE) code of a CTLE to adjust equalization of the equalized information signal.
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17.发明授权公开(公告)号：US10680634B1
公开(公告)日：2020-06-09
申请号：US16378467
申请日：2019-04-08
申请人： Kandou Labs, S.A.
摘要： Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.
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公开(公告)号：US10673608B2
公开(公告)日：2020-06-02
申请号：US16405769
申请日：2019-05-07
申请人： Kandou Labs, S.A.
发明人： Armin Tajalli
摘要： Methods and systems are described for receiving a signal to be sampled and responsively generating, at a pair of common nodes, a differential current representative of the received signal, receiving a plurality of sampling interval signals, each sampling interval signal received at a corresponding sampling phase of a plurality of sampling phases, for each sampling phase, pre-charging a corresponding pair of output nodes using a pre-charging FET pair receiving the sampling interval signal, forming a differential output voltage by discharging the corresponding pair of output nodes via a discharging FET pair connected to the pair of common nodes, the FET pair receiving the sampling interval signal and selectively enabling the differential current to discharge the corresponding pair of output nodes, and latching the differential output voltage.
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公开(公告)号：US10666297B2
公开(公告)日：2020-05-26
申请号：US15954138
申请日：2018-04-16
申请人： Kandou Labs, S.A.
发明人： Amin Shokrollahi , Dario Carnelli
摘要： Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.
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公开(公告)号：US10608850B2
公开(公告)日：2020-03-31
申请号：US16537507
申请日：2019-08-09
申请人： Kandou Labs, S.A.
发明人： Ali Hormati , Armin Tajalli , Amin Shokrollahi
摘要： Transmission of baseband and carrier-modulated vector codewords, using a plurality of encoders, each encoder configured to receive information bits and to generate a set of baseband-encoded symbols representing a vector codeword; one or more modulation circuits, each modulation circuit configured to operate on a corresponding set of baseband-encoded symbols, and using a respective unique carrier frequency, to generate a set of carrier-modulated encoded symbols; and, a summation circuit configured to generate a set of wire-specific outputs, each wire-specific output representing a sum of respective symbols of the carrier-modulated encoded symbols and at least one set of baseband-encoded symbols.
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