公开(公告)号：US20120064678A1

公开(公告)日：2012-03-15

申请号：US13069070

申请日：2011-03-22

Applicant: Byeong-Jin LEE ,  Yu-Gwang Jeong ,  Dong-Ju Yang ,  Bong-Kyun Kim ,  Hong-Sick Park ,  Byeong-Beom Kim ,  Sang-Gab Kim ,  Ji-Young Park ,  Jean-Ho Song ,  Ki-Yeup Lee ,  Shin-Il Choi

Inventor： Byeong-Jin LEE ,  Yu-Gwang Jeong ,  Dong-Ju Yang ,  Bong-Kyun Kim ,  Hong-Sick Park ,  Byeong-Beom Kim ,  Sang-Gab Kim ,  Ji-Young Park ,  Jean-Ho Song ,  Ki-Yeup Lee ,  Shin-Il Choi

IPC: H01L21/336

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78678

Abstract: A method for manufacturing a TFT array panel includes forming a photosensitive film pattern with first and second parts in first and second sections on a metal layer, etching the metal layer of a third section using the film pattern as a mask to form first and second metal patterns, etching the film pattern to remove the first part, etching first and second amorphous silicon layers of the third section using the second part as a mask to form an amorphous silicon pattern and a semiconductor, etching the first and second metal patterns of the first section using the second part as a mask to form a source electrode and a drain electrode including an upper layer and a lower layer, and etching the amorphous silicon pattern of the region corresponding to the first section by using the second part as a mask to form an ohmic contact.

Abstract translation: 一种TFT阵列板的制造方法，其特征在于，在金属层的第一和第二部分中形成具有第一和第二部分的感光膜图案，使用所述膜图案作为掩模蚀刻第三部分的金属层，以形成第一和第二金属 蚀刻薄膜图案以去除第一部分，使用第二部分作为掩模蚀刻第三部分的第一和第二非晶硅层以形成非晶硅图案和半导体，蚀刻第一部分的第一和第二金属图案 使用第二部分作为掩模形成源电极和包括上层和下层的漏极，并且通过使用第二部分作为掩模来蚀刻与第一部分相对应的区域的非晶硅图案以形成 欧姆接触。

公开(公告)号：US20120028421A1

公开(公告)日：2012-02-02

申请号：US13109686

申请日：2011-05-17

Applicant: Dong-Ju YANG ,  Yu-Gwang JEONG ,  Jean-Ho SONG ,  Ki-Yeup LEE ,  Shin-Il CHOI ,  Tae-Woo KIM

Inventor： Dong-Ju YANG ,  Yu-Gwang JEONG ,  Jean-Ho SONG ,  Ki-Yeup LEE ,  Shin-Il CHOI ,  Tae-Woo KIM

IPC: H01L21/336

CPC classification number: H01L27/1288 ,  H01L21/32138 ,  H01L27/1214 ,  H01L27/1255 ,  H01L29/458

Abstract: A method for manufacturing a thin film transistor array panel includes forming a gate line; forming an insulating layer on the gate line; forming first and second silicon layers first and second metal layers; forming a photoresist pattern having first and second portions; forming first and second metal patterns by etching the first and second metal layers; processing the first metal pattern with SF6 or SF6/He; forming silicon and semiconductor patterns by etching the second and first silicon layers; removing the first portion of the photoresist pattern; forming an upper layer of a data wire by wet etching the second metal pattern; forming a lower layer of the data wire and an ohmic contact by etching the first metal and amorphous silicon patterns; forming a passivation layer including a contact hole on the upper layer; and forming a pixel electrode on the passivation layer.

Abstract translation: 薄膜晶体管阵列板的制造方法包括：形成栅极线; 在栅极线上形成绝缘层; 第一和第二硅层第一和第二金属层; 形成具有第一和第二部分的光致抗蚀剂图案; 通过蚀刻第一和第二金属层形成第一和第二金属图案; 用SF6或SF6 / He处理第一金属图案; 通过蚀刻第二和第一硅层形成硅和半导体图案; 去除光致抗蚀剂图案的第一部分; 通过湿法蚀刻第二金属图案形成数据线的上层; 通过蚀刻第一金属和非晶硅图案形成数据线的下层和欧姆接触; 在上层形成包括接触孔的钝化层; 以及在所述钝化层上形成像素电极。

公开(公告)号：US20110297931A1

公开(公告)日：2011-12-08

申请号：US13210282

申请日：2011-08-15

Applicant: Dong-Ju YANG ,  Yu-Gwang JEONG ,  Ki-Yeup LEE ,  Sang-Gab KIM ,  Yun-Jong YEO ,  Shin-Il CHOI ,  Hong-Kee CHIN ,  Seung-Ha CHOI ,  Jung-Suk BANG

Inventor： Dong-Ju YANG ,  Yu-Gwang JEONG ,  Ki-Yeup LEE ,  Sang-Gab KIM ,  Yun-Jong YEO ,  Shin-Il CHOI ,  Hong-Kee CHIN ,  Seung-Ha CHOI ,  Jung-Suk BANG

IPC: H01L29/786

CPC classification number: H01L27/1248 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/7869

Abstract: A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.

Abstract translation: 提出了制造薄膜晶体管阵列基板的方法。 该方法需要在绝缘基板上形成栅极互连线，在栅极互连线上形成栅极绝缘层，在半导体层上形成半导体层和数据互连线，依次形成多个钝化层，将钝化层蚀刻到 作为数据互连线的延伸线的漏电极。 在该阶段暴露的漏电极的部分是漏极电极 - 像素电极接触部分的一部分。 形成连接到漏电极的像素电极。 两个钝化层具有相同的组成，但是在不同的温度下进行处理。 还提出了以上述方式制备的薄膜晶体管。

公开(公告)号：US08017459B2

公开(公告)日：2011-09-13

申请号：US12484116

申请日：2009-06-12

Applicant: Dong-Ju Yang ,  Yu-Gwang Jeong ,  Ki-Yeup Lee ,  Sang-Gab Kim ,  Yun-Jong Yeo ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Jung-Suk Bang

Inventor： Dong-Ju Yang ,  Yu-Gwang Jeong ,  Ki-Yeup Lee ,  Sang-Gab Kim ,  Yun-Jong Yeo ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Jung-Suk Bang

IPC: H01L21/00

CPC classification number: H01L27/1248 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/7869

Abstract: A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.

Abstract translation: 提出了制造薄膜晶体管阵列基板的方法。 该方法需要在绝缘基板上形成栅极互连线，在栅极互连线上形成栅极绝缘层，在半导体层上形成半导体层和数据互连线，依次形成多个钝化层，将钝化层蚀刻到 作为数据互连线的延伸线的漏电极。 在该阶段暴露的漏电极的部分是漏极电极 - 像素电极接触部分的一部分。 形成连接到漏电极的像素电极。 两个钝化层具有相同的组成，但是在不同的温度下进行处理。 还提出了以上述方式制备的薄膜晶体管。

公开(公告)号：US20110051057A1

公开(公告)日：2011-03-03

申请号：US12874068

申请日：2010-09-01

Applicant: Ki-Yong Song ,  Ki-Yeup Lee ,  Jae-Hong Kim ,  Yoon-Ho Kang ,  Yong-Hwan Kim

Inventor： Ki-Yong Song ,  Ki-Yeup Lee ,  Jae-Hong Kim ,  Yoon-Ho Kang ,  Yong-Hwan Kim

IPC: G02F1/1335 ,  B05D3/06 ,  B05D3/14

CPC classification number: G02F1/1393 ,  G02F1/133512 ,  G02F1/133788 ,  G02F2001/13775 ,  G02F2201/086

Abstract: The present invention relates to a liquid crystal display, wherein arrangement of liquid crystal molecules thereof is controlled by using a monomer that is polymerized by ultraviolet rays to provide a pre-tilt. To prevent damage to organic material layers when irradiating ultraviolet rays to the monomer, a blocking film made of an ultraviolet absorbing agent is formed on or over at least one such layer.

Abstract translation: 本发明涉及一种液晶显示器，其中通过使用通过紫外线聚合的单体来提供预倾角来控制其液晶分子的排列。 为了防止在向单体照射紫外线时损坏有机材料层，在至少一层这样的层上形成有由紫外线吸收剂形成的阻挡膜。

公开(公告)号：US06171938B2

公开(公告)日：2001-01-09

申请号：US09342093

申请日：1999-06-29

Applicant: Ki Yeup Lee ,  Jeong Woo Ha

Inventor： Ki Yeup Lee ,  Jeong Woo Ha

IPC: H01L214763

CPC classification number: H01L29/66583 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76814 ,  Y10S438/963

Abstract: The present invention is to provide a method for fabricating a semiconductor device, including the steps of: (a) forming an insulating layer on a semiconductor substrate; (b) selectively removing the insulating layer and then forming an opening and the residual insulating layer on a bottom of the opening; (c) removing the residual insulating layer by wet etching in order to expose the semiconductor substrate; and (d) burying a conductive layer in the opening and then forming a conductive layer pattern connected to the semiconductor substrate.

Abstract translation: 本发明提供一种制造半导体器件的方法，包括以下步骤：（a）在半导体衬底上形成绝缘层; （b）选择性地去除所述绝缘层，然后在所述开口的底部上形成开口和所述残留绝缘层; （c）通过湿蚀刻去除残留绝缘层，以露出半导体衬底; 和（d）将导电层埋在开口中，然后形成连接到半导体衬底的导电层图案。

公开(公告)号：US08586990B2

公开(公告)日：2013-11-19

申请号：US13210282

申请日：2011-08-15

Applicant: Dong-Ju Yang ,  Yu Gwang Jeong ,  Ki-Yeup Lee ,  Sang-Gab Kim ,  Yun-Jong Yeo ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Jung-Suk Bang

Inventor： Dong-Ju Yang ,  Yu Gwang Jeong ,  Ki-Yeup Lee ,  Sang-Gab Kim ,  Yun-Jong Yeo ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Jung-Suk Bang

IPC: H01L27/14

CPC classification number: H01L27/1248 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/7869

Abstract: A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.

Abstract translation: 提出了制造薄膜晶体管阵列基板的方法。 该方法需要在绝缘基板上形成栅极互连线，在栅极互连线上形成栅极绝缘层，在半导体层上形成半导体层和数据互连线，依次形成多个钝化层，将钝化层蚀刻到 作为数据互连线的延伸线的漏电极。 在该阶段暴露的漏电极的部分是漏极电极 - 像素电极接触部分的一部分。 形成连接到漏电极的像素电极。 两个钝化层具有相同的组成，但是在不同的温度下进行处理。 还提出了以上述方式制备的薄膜晶体管。

公开(公告)号：US08450737B2

公开(公告)日：2013-05-28

申请号：US12784376

申请日：2010-05-20

Applicant: Shin-Il Choi ,  Yu-Gwang Jeong ,  Ki-Yeup Lee ,  Dong-Ju Yang ,  Jean-Ho Song

Inventor： Shin-Il Choi ,  Yu-Gwang Jeong ,  Ki-Yeup Lee ,  Dong-Ju Yang ,  Jean-Ho Song

IPC: H01L31/00

CPC classification number: H01L27/124 ,  H01L27/1248 ,  H01L27/1288

Abstract: A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.

Abstract translation: 薄膜晶体管阵列面板包括：基板; 设置在基板上并包括铜（Cu）的信号线; 钝化层，设置在所述信号线上并具有暴露所述信号线的一部分的接触孔; 以及设置在所述钝化层上并通过所述接触孔连接到所述信号线的所述部分的导电层，其中所述钝化层包括包含不包含硫的有机绝缘体的有机钝化层，以及制造所述薄膜的方法 晶体管防止在信号线上形成异物。

公开(公告)号：US20110140111A1

公开(公告)日：2011-06-16

申请号：US12859792

申请日：2010-08-20

Applicant: Chang-Oh JEONG ,  Woo-Sung SOHN ,  Dong-Gyu KIM ,  Shi-Yul KIM ,  Ki-Yeup LEE ,  Jean-Ho SONG

Inventor： Chang-Oh JEONG ,  Woo-Sung SOHN ,  Dong-Gyu KIM ,  Shi-Yul KIM ,  Ki-Yeup LEE ,  Jean-Ho SONG

IPC: H01L33/08 ,  H01L21/336

CPC classification number: H01L33/16 ,  H01L27/124 ,  H01L27/1288

Abstract: A thin film transistor array panel is provided and includes a gate line, a gate insulating layer covering the gate line, a semiconductor layer disposed on the gate insulating layer, and a data line and a drain electrode disposed on the semiconductor layer. The data line and the drain electrode have a dual-layered structure including a lower layer and an upper layer with the lower layer having a first portion protruded outside the upper layer and the semiconductor layer having a second portion protruded outside the edge of the lower layer.

Abstract translation: 提供了一种薄膜晶体管阵列面板，包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，以及设置在半导体层上的数据线和漏电极。 数据线和漏电极具有包括下层和上层的双层结构，其中下层具有突出于上层之外的第一部分，并且半导体层具有突出于下层边缘外侧的第二部分 。

公开(公告)号：US20110089421A1

公开(公告)日：2011-04-21

申请号：US12784376

申请日：2010-05-20

Applicant: Shin-Il CHOI ,  Yu-Gwang Jeong ,  Ki-Yeup Lee ,  Dong-Ju Yang ,  Jean-Ho Song

Inventor： Shin-Il CHOI ,  Yu-Gwang Jeong ,  Ki-Yeup Lee ,  Dong-Ju Yang ,  Jean-Ho Song

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/782

CPC classification number: H01L27/124 ,  H01L27/1248 ,  H01L27/1288

Abstract: A thin film transistor array panel includes: a substrate; a signal line disposed on the substrate and including copper (Cu); a passivation layer disposed on the signal line and having a contact hole exposing a portion of the signal line; and a conductive layer disposed on the passivation layer and connected to the portion of the signal line through the contact hole, wherein the passivation layer includes an organic passivation layer including an organic insulator that does not include sulfur, and a method of manufacturing the thin film transistor prevents formation of foreign particles on the signal line.

Abstract translation: 薄膜晶体管阵列面板包括：基板; 设置在基板上并包括铜（Cu）的信号线; 钝化层，设置在所述信号线上并具有暴露所述信号线的一部分的接触孔; 以及设置在所述钝化层上并通过所述接触孔连接到所述信号线的所述部分的导电层，其中所述钝化层包括包含不包含硫的有机绝缘体的有机钝化层，以及制造所述薄膜的方法 晶体管防止在信号线上形成异物。