公开(公告)号：US20110140111A1

公开(公告)日：2011-06-16

申请号：US12859792

申请日：2010-08-20

申请人： Chang-Oh JEONG ,  Woo-Sung SOHN ,  Dong-Gyu KIM ,  Shi-Yul KIM ,  Ki-Yeup LEE ,  Jean-Ho SONG

发明人： Chang-Oh JEONG ,  Woo-Sung SOHN ,  Dong-Gyu KIM ,  Shi-Yul KIM ,  Ki-Yeup LEE ,  Jean-Ho SONG

IPC分类号： H01L33/08 ,  H01L21/336

CPC分类号： H01L33/16 ,  H01L27/124 ,  H01L27/1288

摘要： A thin film transistor array panel is provided and includes a gate line, a gate insulating layer covering the gate line, a semiconductor layer disposed on the gate insulating layer, and a data line and a drain electrode disposed on the semiconductor layer. The data line and the drain electrode have a dual-layered structure including a lower layer and an upper layer with the lower layer having a first portion protruded outside the upper layer and the semiconductor layer having a second portion protruded outside the edge of the lower layer.

摘要翻译： 提供了一种薄膜晶体管阵列面板，包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，以及设置在半导体层上的数据线和漏电极。 数据线和漏电极具有包括下层和上层的双层结构，其中下层具有突出于上层之外的第一部分，并且半导体层具有突出于下层边缘外侧的第二部分 。

公开(公告)号：US20080248617A1

公开(公告)日：2008-10-09

申请号：US12123858

申请日：2008-05-20

申请人： Chang-Oh JEONG ,  Hong-Sick PARK ,  Shi-Yul KIM ,  Sang-Gab KIM

发明人： Chang-Oh JEONG ,  Hong-Sick PARK ,  Shi-Yul KIM ,  Sang-Gab KIM

IPC分类号： H01L21/331

CPC分类号： G02F1/136286 ,  G02F2001/133397 ,  G02F2001/13629 ,  G02F2201/501 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/42384

摘要： A display substrate includes a base substrate, a first metal pattern, a gate insulating layer, a second metal pattern, a channel layer and a pixel electrode. The first metal pattern is formed on the base substrate, and includes a gate line and a gate electrode of a switching element. The gate insulating layer is formed on the base substrate including the first metal pattern. The second metal pattern is formed on the gate insulating layer, and includes a source electrode, a drain electrode and a source line. The channel layer is formed under the second metal pattern, and is patterned to have substantially a same side surface as a side surface of the second metal pattern. The pixel electrode is electrically connected to the drain electrode. Therefore, an afterimage on a display panel, thus improving display quality.

摘要翻译： 显示基板包括基底基板，第一金属图案，栅极绝缘层，第二金属图案，沟道层和像素电极。 第一金属图案形成在基底基板上，并且包括开关元件的栅极线和栅电极。 栅极绝缘层形成在包括第一金属图案的基底基板上。 第二金属图案形成在栅极绝缘层上，并且包括源电极，漏电极和源极线。 沟道层形成在第二金属图案之下，并且被图案化以具有与第二金属图案的侧表面大致相同的侧表面。 像素电极电连接到漏电极。 因此，在显示面板上留下余像，从而提高显示质量。

公开(公告)号：US20120043545A1

公开(公告)日：2012-02-23

申请号：US13010656

申请日：2011-01-20

申请人： Hyung-Jun KIM ,  Chang-Oh JEONG ,  Jae-Hong KIM

发明人： Hyung-Jun KIM ,  Chang-Oh JEONG ,  Jae-Hong KIM

IPC分类号： H01L29/12 ,  H01L21/336

CPC分类号： H01L29/6675 ,  G02F1/136213 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L27/124 ,  H01L29/42384

摘要： A thin film transistor display panel includes a substrate, a gate wire on the substrate and including a gate line and a gate electrode; a gate insulating layer on the gate wire; a semiconductor layer on the gate insulating layer; a data wire including a source electrode on the semiconductor layer, a drain electrode opposing the source electrode with respect to the gate electrode, and a data line; a passivation layer on the data wire having a contact hole exposing the drain electrode; and a pixel electrode on the passivation layer and connected to the drain electrode through the contact hole. The gate wire has a first region and second region where the gate line and the gate electrode are positioned, respectively. The thickness of the gate wire in the first region is greater than the thickness of the gate wire in the second region.

摘要翻译： 薄膜晶体管显示面板包括衬底，衬底上的栅极线，并且包括栅极线和栅电极; 栅极线上的栅极绝缘层; 栅极绝缘层上的半导体层; 数据线，包括半导体层上的源电极，与源电极相对于栅电极相对的漏电极和数据线; 数据线上的钝化层具有暴露漏电极的接触孔; 以及钝化层上的像素电极，并通过接触孔与漏电极连接。 栅极线分别具有栅极线和栅电极所在的第一区域和第二区域。 第一区域中的栅极线的厚度大于第二区域中的栅极线的厚度。

公开(公告)号：US20100149476A1

公开(公告)日：2010-06-17

申请号：US12534300

申请日：2009-08-03

申请人： Do-Hyun KIM ,  Jong-Hyun CHOUNG ,  Young-Joo CHOI ,  Hong-Sick PARK ,  Tae-Hyung IHN ,  Dong-Hoon LEE ,  Pil-Sang YUN ,  Je-Hyeong PARK ,  Chang-Oh JEONG ,  Je-Hun LEE ,  Sun-Young HONG ,  Bong-Kyun KIM ,  Byeong-Jin LEE ,  Nam-Seok SUH

发明人： Do-Hyun KIM ,  Jong-Hyun CHOUNG ,  Young-Joo CHOI ,  Hong-Sick PARK ,  Tae-Hyung IHN ,  Dong-Hoon LEE ,  Pil-Sang YUN ,  Je-Hyeong PARK ,  Chang-Oh JEONG ,  Je-Hun LEE ,  Sun-Young HONG ,  Bong-Kyun KIM ,  Byeong-Jin LEE ,  Nam-Seok SUH

IPC分类号： G02F1/1333 ,  B05D5/12 ,  B44C1/22

CPC分类号： G02F1/136286 ,  G02F2001/133302 ,  G02F2001/136295

摘要： A display substrate includes; a base substrate, a deformation preventing layer disposed on a lower surface of the base substrate, wherein the deformation preventing layer applies a force to the base substrate to prevent the base substrate from bending, a gate line disposed on an upper surface of the base substrate, a data line disposed on the base substrate, and a pixel electrode disposed on the base substrate.

摘要翻译： 显示基板包括： 基底基板，设置在基底基板的下表面的变形防止层，其中变形防止层向基底基板施加力以防止基底基板弯曲，设置在基底基板的上表面上的栅极线 设置在基底基板上的数据线，以及配置在基底基板上的像素电极。

公开(公告)号：US20080099765A1

公开(公告)日：2008-05-01

申请号：US11923914

申请日：2007-10-25

申请人： Do-Hyun KIM ,  Je-Hun LEE ,  Chang-Oh JEONG

发明人： Do-Hyun KIM ,  Je-Hun LEE ,  Chang-Oh JEONG

IPC分类号： H01L29/04 ,  H01L21/336

CPC分类号： H01L29/4908 ,  H01L27/124 ,  H01L29/458

摘要： A thin film transistor substrate and fabricating method thereof, the thin film transistor substrate including a substrate, a gate line and a gate electrode, each including a metal adhesion layer and a Cu alloy layer disposed on the substrate, an active layer and an ohmic contact layer disposed over the gate electrode, a gate insulating layer disposed between the gate electrode and the active and ohmic contact layers, source and drain electrodes disposed on the ohmic contact layer, and a data line connected to the source electrode.

摘要翻译： 一种薄膜晶体管基板及其制造方法，所述薄膜晶体管基板包括基板，栅极线和栅电极，每个薄膜晶体管基板包括设置在基板上的金属粘合层和Cu合金层，有源层和欧姆接触 设置在栅极电极上的栅极绝缘层，设置在栅电极与有源欧姆接触层之间的栅极绝缘层，设置在欧姆接触层上的源电极和漏电极以及连接到源电极的数据线。

公开(公告)号：US20080017862A1

公开(公告)日：2008-01-24

申请号：US11779534

申请日：2007-07-18

申请人： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-Oh JEONG

发明人： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-Oh JEONG

IPC分类号： H01L29/04 ,  H01L21/00

CPC分类号： G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/124

摘要： An array substrate includes a switching element, a signal transmission line, a passivation layer and a pixel electrode. The switching element is disposed on an insulating substrate. The signal transmission line is connected to the switching element and includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is disposed on the insulating substrate. The conductive line is disposed on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The passivation layer covers the switching element and the signal transmission line and has a contact hole through which a drain electrode of the switching element is partially exposed. The pixel electrode is disposed on the insulating substrate, and is connected to the drain electrode of the switching element through the contact hole.

摘要翻译： 阵列基板包括开关元件，信号传输线，钝化层和像素电极。 开关元件设置在绝缘基板上。 信号传输线连接到开关元件，并且包括阻挡层，导电线和氮化铜层。 阻挡层设置在绝缘基板上。 导电线设置在阻挡层上并且包括铜或铜合金。 氮化铜层覆盖导电线。 钝化层覆盖开关元件和信号传输线，并且具有接触孔，开关元件的漏电极通过该接触孔部分露出。 像素电极设置在绝缘基板上，并通过接触孔与开关元件的漏电极连接。

公开(公告)号：US20110309510A1

公开(公告)日：2011-12-22

申请号：US13222558

申请日：2011-08-31

申请人： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-Oh JEONG

发明人： Je-Hun LEE ,  Do-Hyun KIM ,  Eun-Guk LEE ,  Chang-Oh JEONG

IPC分类号： H01L23/482

CPC分类号： G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/124

摘要： An array substrate includes a switching element, a signal transmission line, a passivation layer and a pixel electrode. The switching element is disposed on an insulating substrate. The signal transmission line is connected to the switching element and includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is disposed on the insulating substrate. The conductive line is disposed on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The passivation layer covers the switching element and the signal transmission line and has a contact hole through which a drain electrode of the switching element is partially exposed. The pixel electrode is disposed on the insulating substrate, and is connected to the drain electrode of the switching element through the contact hole.

摘要翻译： 阵列基板包括开关元件，信号传输线，钝化层和像素电极。 开关元件设置在绝缘基板上。 信号传输线连接到开关元件，并且包括阻挡层，导电线和氮化铜层。 阻挡层设置在绝缘基板上。 导电线设置在阻挡层上并且包括铜或铜合金。 氮化铜层覆盖导电线。 钝化层覆盖开关元件和信号传输线，并且具有接触孔，开关元件的漏电极通过该接触孔部分露出。 像素电极设置在绝缘基板上，并通过接触孔与开关元件的漏电极连接。

公开(公告)号：US20080227245A1

公开(公告)日：2008-09-18

申请号：US12112104

申请日：2008-04-30

申请人： Jae-Gab LEE ,  Bong-Joo KANG ,  Beom-Seok CHO ,  Chang-Oh JEONG

发明人： Jae-Gab LEE ,  Bong-Joo KANG ,  Beom-Seok CHO ,  Chang-Oh JEONG

IPC分类号： H01L21/84

CPC分类号： H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66765

摘要： A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.

摘要翻译： 薄膜晶体管阵列面板包括绝缘基板，形成在绝缘基板上的栅极线。 栅极绝缘层覆盖栅极线。 在栅极绝缘层上形成半导体图形。 在栅极绝缘层和半导体图案上形成具有源电极，漏电极和数据线的数据线。 在数据线上形成保护层。 在保护层上形成通过接触孔与漏电极连接的像素电极。 栅极线和数据线由含有Ag的Ag合金和包含选自Zn，In，Sn和Cr中的至少一种的添加剂制成。

公开(公告)号：US20080079006A1

公开(公告)日：2008-04-03

申请号：US11850922

申请日：2007-09-06

申请人： Hong-Sick PARK ,  Bong-Kyun KIM ,  Chang-Oh JEONG ,  Jong-Hyun CHOUNG ,  Sun-Young HONG ,  Won-Suk SHIN ,  Byeong-Jin LEE

发明人： Hong-Sick PARK ,  Bong-Kyun KIM ,  Chang-Oh JEONG ,  Jong-Hyun CHOUNG ,  Sun-Young HONG ,  Won-Suk SHIN ,  Byeong-Jin LEE

IPC分类号： H01L29/04 ,  C09K13/08 ,  H01L21/00 ,  H01L23/52

CPC分类号： C09K13/08 ,  G09G2300/0426 ,  G09G2300/0439 ,  G09G2320/0223 ,  H01L23/53238 ,  H01L27/124 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

摘要： A thin film panel includes a substrate, a gate line formed on the substrate, a gate insulating layer formed on the gate line, a semiconductor layer formed on the gate insulating layer, a data line, including a source electrode, and a drain electrode formed on the gate insulating layer or the semiconductor layer, and a pixel electrode connected to the drain electrode, wherein at least one of the gate line and the data line and drain electrode includes a first conductive layer made of a molybdenum Mo-niobium Nb alloy and a second conductive layer made of a copper Cu-containing metal.

摘要翻译： 薄膜面板包括基板，形成在基板上的栅极线，形成在栅极线上的栅极绝缘层，形成在栅极绝缘层上的半导体层，包括源电极的数据线和形成的漏电极 在所述栅极绝缘层或所述半导体层上形成的像素电极和与所述漏极连接的像素电极，其中所述栅极线和所述数据线和漏极的至少一个包括由钼Mo-Nb铌合金构成的第一导电层，以及 由含铜铜金属制成的第二导电层。

公开(公告)号：US20120052638A1

公开(公告)日：2012-03-01

申请号：US13191833

申请日：2011-07-27

申请人： Hyung-Jun KIM ,  Chang-Oh JEONG ,  Il-Yong YOON

发明人： Hyung-Jun KIM ,  Chang-Oh JEONG ,  Il-Yong YOON

IPC分类号： H01L21/336

CPC分类号： H01L21/268 ,  H01L21/02675 ,  H01L21/02678 ,  H01L27/1229 ,  H01L27/1274 ,  H01L29/66765 ,  H01L29/78696

摘要： A method of fabricating a thin-film transistor (TFT) substrate includes forming a gate electrode on a substrate; forming an insulating film on the gate electrode; forming an amorphous semiconductor pattern on the insulating film; and forming a source electrode separated from a drain electrode on the amorphous semiconductor pattern; forming a light-concentrating layer, which includes a protrusion, on the amorphous semiconductor pattern, the source electrode, and the drain electrode; and crystallizing at least part of the amorphous semiconductor pattern by irradiating light to the protrusion of the light-concentrating layer.

摘要翻译： 制造薄膜晶体管（TFT）基板的方法包括在基板上形成栅电极; 在栅电极上形成绝缘膜; 在所述绝缘膜上形成非晶半导体图案; 以及形成与所述非晶半导体图案上的漏电极分离的源电极; 在所述非晶半导体图案，所述源电极和所述漏电极上形成包括突起的聚光层; 以及通过向所述聚光层的所述突起照射光而使所述非晶半导体图案的至少一部分结晶。