公开(公告)号：US20110164445A1

公开(公告)日：2011-07-07

申请号：US13052439

申请日：2011-03-21

Applicant: Ki-Tae PARK

Inventor： Ki-Tae PARK

IPC: G11C5/02

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/025 ,  G11C5/143 ,  G11C7/20

Abstract: A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips

Abstract translation: 半导体存储器件包括多个存储器芯片，每个存储器芯片包括芯片识别（ID）产生电路。 各个存储器芯片的芯片ID生成电路以级联配置可操作地连接在一起，并且芯片ID生成电路响应于施加电源电压而被激活，存储器件顺序地生成多个 设备芯片

公开(公告)号：US20110090738A1

公开(公告)日：2011-04-21

申请号：US12977419

申请日：2010-12-23

Applicant: Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

Inventor： Ki-Tae Park ,  Jung-Dal Choi ,  Jong-Sun Sel ,  Yoo-Cheol Shin

IPC: G11C16/12

CPC classification number: G11C16/0483 ,  G11C16/107 ,  G11C16/12 ,  G11C16/3445

Abstract: A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.

Abstract translation: NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压 到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。 在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。 在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

公开(公告)号：US07916542B2

公开(公告)日：2011-03-29

申请号：US12236771

申请日：2008-09-24

Applicant: Ki-Tae Park ,  Hyun-Kyoung Kim

Inventor： Ki-Tae Park ,  Hyun-Kyoung Kim

IPC: G11C11/34

CPC classification number: G11C16/3418

Abstract: A nonvolatile memory device includes a memory cell array having multiple memory cells arranged at intersections of word lines and bit lines, a first page region configured with at least two adjacent memory cells coupled to a word line, and a second page region configured with at least two adjacent memory cells coupled to the word line. The nonvolatile memory devices also includes a first common source line connecting with the memory cells of the first page region, and a second common source line connecting with the memory cells of the second page region. The first and second common source lines are controlled independently.

Abstract translation: 非易失性存储器件包括存储单元阵列，其具有布置在字线和位线的交点处的多个存储器单元，配置有耦合到字线的至少两个相邻存储器单元的第一页区域和至少配置有第二页区域 耦合到字线的两个相邻的存储单元。 非易失性存储器件还包括与第一页区域的存储单元连接的第一公共源极线和与第二页区域的存储器单元连接的第二公共源极线。 第一和第二公共源极线独立控制。

公开(公告)号：US07843733B2

公开(公告)日：2010-11-30

申请号：US12136933

申请日：2008-06-11

Applicant: Doo-gon Kim ,  Ki-tae Park ,  Yeong-taek Lee

Inventor： Doo-gon Kim ,  Ki-tae Park ,  Yeong-taek Lee

IPC: G11C16/04

CPC classification number: G11C16/3418

Abstract: Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled.

Abstract translation: 提供闪存器件，其包括垂直堆叠的多个层。 多个层中的每一个包括多个存储单元。 行解码器电耦合到多个层并且被配置为向多个层提供字线电压。 提供在多个层中的至少两层中的存储单元属于相同的存储块，并且与多个层中的至少两个层中的存储单元相关联的字线电耦合。

公开(公告)号：US07830724B2

公开(公告)日：2010-11-09

申请号：US12636980

申请日：2009-12-14

Applicant: Ki-Tae Park ,  Jung-Dal Choi

Inventor： Ki-Tae Park ,  Jung-Dal Choi

IPC: G11C16/04

CPC classification number: G11C8/08 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/3418

Abstract: A nonvolatile memory device comprises a memory cell array wherein a plurality of memory cell transistors are divided into multiple erase blocks. The multiple erase blocks are separated from each other by dummy word lines. During an erase operation of one of the multiple blocks, a dummy word line separating the one of the multiple blocks from other erase blocks is driven with a coupling inhibition voltage.

Abstract translation: 非易失性存储器件包括存储单元阵列，其中多个存储单元晶体管被分成多个擦除块。 多个擦除块通过虚拟字线彼此分离。 在多个块之一的擦除操作期间，以耦合禁止电压驱动将多个块中的一个与其它擦除块分开的虚拟字线。

公开(公告)号：US20100265769A1

公开(公告)日：2010-10-21

申请号：US12823726

申请日：2010-06-25

Applicant: SOON WOOK HWANG ,  Ki Tae Park ,  Yeong Taek Lee

Inventor： SOON WOOK HWANG ,  Ki Tae Park ,  Yeong Taek Lee

IPC: G11C16/04

CPC classification number: G11C16/08 ,  G11C7/227 ,  G11C16/0483

Abstract: An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal.

Abstract translation: 电可擦除可编程非易失性半导体存储器件。 半导体存储器件包括存储单元阵列，其包括多个存储块，每个存储块包括多个存储器单元，一个虚拟存储单元和一个选择栅极晶体管。 每个具有连接在对应的字线使能信号线和相应的字线之间的电流路径的传输晶体管由块选择电路的输出控制。 转移晶体管包括电耦合到虚拟存储器单元的虚拟转移晶体管，并且被配置为发送伪字线使能信号。

公开(公告)号：US07787306B2

公开(公告)日：2010-08-31

申请号：US12172904

申请日：2008-07-14

Applicant: Jung-Hoon Park ,  Sung-Soo Lee ,  Young-Ho Lim ,  Chang-Sub Lee ,  Ki-Tae Park

Inventor： Jung-Hoon Park ,  Sung-Soo Lee ,  Young-Ho Lim ,  Chang-Sub Lee ,  Ki-Tae Park

IPC: G11C16/06

CPC classification number: G11C16/3418 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427

Abstract: A method of reading a flash memory device can include driving a selected word line by applying a selection voltage thereto and driving unselected word lines by applying a first voltage thereto, driving the unselected word lines and first and second selection lines by applying a second voltage that is higher than the first voltage thereto, and reading data from a memory cell that is coupled to the selected word line.

Abstract translation: 一种读取闪速存储器件的方法可以包括通过向其施加选择电压来驱动所选择的字线并通过向其施加第一电压来驱动未选择的字线，通过施加第二电压来驱动未选择的字线和第一和第二选择线， 高于其第一电压，并且从耦合到所选字线的存储单元读取数据。

公开(公告)号：US07755944B2

公开(公告)日：2010-07-13

申请号：US12142460

申请日：2008-06-19

Applicant: Soon-Wook Hwang ,  Ki-Tae Park ,  Yeong-Taek Lee

Inventor： Soon-Wook Hwang ,  Ki-Tae Park ,  Yeong-Taek Lee

IPC: G11C16/04

CPC classification number: G11C16/08 ,  G11C7/227 ,  G11C16/0483

Abstract: An electrically erasable programmable non-volatile semiconductor memory device. The semiconductor memory device includes a memory cell array comprising a plurality of memory blocks, each memory block comprising a plurality of memory cells, a dummy memory cell, and a select gate transistor. Transfer transistors each having a current path connected between a corresponding wordline enable signal line and a corresponding wordline are controlled by an output of a block selection circuit. The transfer transistors include a dummy transfer transistor electrically coupled to the dummy memory cell, and configured to transmit a dummy wordline enable signal.

Abstract translation: 电可擦除可编程非易失性半导体存储器件。 半导体存储器件包括存储单元阵列，其包括多个存储块，每个存储块包括多个存储器单元，一个虚拟存储单元和一个选择栅极晶体管。 每个具有连接在对应的字线使能信号线和相应的字线之间的电流路径的传输晶体管由块选择电路的输出控制。 转移晶体管包括电耦合到虚拟存储器单元的虚拟转移晶体管，并且被配置为发送伪字线使能信号。

公开(公告)号：US20100067305A1

公开(公告)日：2010-03-18

申请号：US12509612

申请日：2009-07-27

Applicant: Ki-Tae PARK ,  Yeong-Taek LEE ,  Soon-Wook HWANG ,  Young-Wook JEONG

Inventor： Ki-Tae PARK ,  Yeong-Taek LEE ,  Soon-Wook HWANG ,  Young-Wook JEONG

IPC: G11C16/04 ,  G11C5/14

CPC classification number: G11C16/12 ,  G11C16/0483

Abstract: A flash memory and programming method are disclosed. The flash memory includes a memory cell array having memory cells arranged in a plurality of word lines including a selected word line and a plurality of non-selected word lines and a plurality of bit lines, a high voltage generator generating a program voltage applied to the selected word line, and a pass voltage applied to at least one of the non-selected word lines adjacent to the selected word line, and control logic controlling the generation of the program voltage, such that the program voltage is incrementally increased during a program operation, and generation of the pass voltage, such that the program voltage is incrementally increased.

Abstract translation: 公开了闪存和编程方法。 闪速存储器包括存储单元阵列，该存储单元阵列具有布置在包括所选择的字线和多个未选择的字线和多个位线的多个字线中的存储器单元，高电压发生器产生施加到该字线的编程电压 所选择的字线和施加到与所选字线相邻的未选择的字线中的至少一个的通过电压，以及控制逻辑，以控制编程电压的产生，使得编程电压在编程操作期间递增地增加 ，并产生通过电压，使得编程电压递增地增加。

公开(公告)号：US20100027309A1

公开(公告)日：2010-02-04

申请号：US12360138

申请日：2009-01-27

Applicant: Ki-Tae PARK

Inventor： Ki-Tae PARK

IPC: G11C5/06 ,  G11C5/14

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/025 ,  G11C5/143 ,  G11C7/20

Abstract: A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit. The chip ID generation circuits of the respective memory chips are operatively connected together in a cascade configuration, and the chip ID generation circuits are activated in response to application of a power supply voltage the memory device to sequentially generate respective chip ID numbers of the plurality of device chips

Abstract translation: 半导体存储器件包括多个存储器芯片，每个存储器芯片包括芯片识别（ID）产生电路。 各个存储器芯片的芯片ID生成电路以级联配置可操作地连接在一起，并且芯片ID生成电路响应于施加电源电压而被激活，存储器件顺序地生成多个 设备芯片