公开(公告)号：US07920419B2

公开(公告)日：2011-04-05

申请号：US12362914

申请日：2009-01-30

Applicant: Prashant Damle ,  Krishna Parat ,  Shafqat Ahmed

Inventor： Prashant Damle ,  Krishna Parat ,  Shafqat Ahmed

IPC: G11C16/04

CPC classification number: G11C16/3418 ,  G11C16/0483 ,  G11C16/3427 ,  H01L27/11519 ,  H01L27/11524

Abstract: A memory device and a method to prevent or reduce program disturb by isolating P-wells of strings in a non-volatile memory array. During a program operation, the isolated P-wells may be coupled to corresponding bitlines, which may be selected or inhibited, and may be at different voltages. During erase, read, and verify operations, the isolated P-wells may be coupled to source.

Abstract translation: 一种存储器件和通过将非易失性存储器阵列中的P阱分离来防止或减少编程干扰的方法。 在编程操作期间，分离的P阱可以耦合到可以被选择或禁止的相应位线，并且可以处于不同的电压。 在擦除，读取和验证操作期间，隔离的P阱可以耦合到源。

公开(公告)号：US20100155807A1

公开(公告)日：2010-06-24

申请号：US12317535

申请日：2008-12-24

Applicant: Pranav Kalavade ,  Krishna Parat ,  Ervin Hill ,  Kiran Pangal

Inventor： Pranav Kalavade ,  Krishna Parat ,  Ervin Hill ,  Kiran Pangal

IPC: H01L29/788 ,  H01L21/4763 ,  G11C11/34

CPC classification number: G11C16/0416 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

Abstract: Embodiments of an apparatus and methods for providing improved flash memory cell characteristics are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 本文通常描述用于提供改进的闪速存储器单元特性的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20100110795A1

公开(公告)日：2010-05-06

申请号：US12262410

申请日：2008-10-31

Applicant: Satoru Tamada ,  Neal R. Mielke ,  Krishna Parat

Inventor： Satoru Tamada ,  Neal R. Mielke ,  Krishna Parat

IPC: G11C16/06

CPC classification number: G11C16/24 ,  G11C16/10 ,  G11C16/3427

Abstract: A method and device using bitline-bitline capacitance between adjacent bitlines to boost seed voltage in a memory device are provided. The method may include a precharge phase, a boost phase, an equalize phase, and a lock in phase. In one embodiment, the method may include boosting the seed voltage twice. The bitlines may be divided into one or more segments.

Abstract translation: 提供了一种在相邻位线之间使用位线位线电容以提高存储器件中的种子电压的方法和装置。 该方法可以包括预充电阶段，升压阶段，均衡阶段和同相锁定。 在一个实施例中，该方法可以包括两次提升种子电压。 位线可以分为一个或多个段。

公开(公告)号：US06943071B2

公开(公告)日：2005-09-13

申请号：US10162173

申请日：2002-06-03

Applicant: Albert Fazio ,  Krishna Parat ,  Glen Wada ,  Neal Mielke ,  Rex Stone

Inventor： Albert Fazio ,  Krishna Parat ,  Glen Wada ,  Neal Mielke ,  Rex Stone

IPC: H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L21/8238

CPC classification number: H01L27/11526 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76897 ,  H01L27/115 ,  H01L27/11536 ,  H01L29/66825 ,  H01L29/7883

Abstract: A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.

Abstract translation: 一种非易失性存储单元，包括形成在衬底中并限定衬底有源区的一对间隔开的浅沟槽隔离区。 隧道电介质形成在衬底有源区上。 浮动栅极形成在隧道电介质上，并且在间隔开的浅沟槽隔离区域之间自对准。 介电层形成在浮栅上，形成在电介质层上的控制栅。 源极区域和漏极区域形成在浮置栅极的相对侧上的衬底有源区域中。

公开(公告)号：US06518618B1

公开(公告)日：2003-02-11

申请号：US09454683

申请日：1999-12-03

Applicant: Albert Fazio ,  Krishna Parat ,  Glen Wada ,  Neal Mielke ,  Rex Stone

Inventor： Albert Fazio ,  Krishna Parat ,  Glen Wada ,  Neal Mielke ,  Rex Stone

IPC: H01L2972

CPC classification number: H01L27/11526 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/76897 ,  H01L27/115 ,  H01L27/11536 ,  H01L29/66825 ,  H01L29/7883

Abstract: A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.

公开(公告)号：US5825603A

公开(公告)日：1998-10-20

申请号：US921809

申请日：1997-09-02

Applicant: Krishna Parat ,  Timothy J. Maloney

Inventor： Krishna Parat ,  Timothy J. Maloney

IPC: H02H9/04 ,  H02H3/22

CPC classification number: H02H9/046

Abstract: An arrangement for preventing damage to a circuit of an integrated circuit due to the occurrence of voltage transients introduced externally to the integrated circuit. According to one embodiment, the voltage transients are due to electrostatic discharge (ESD). The arrangement comprises a latch for coupling to an input pad of the integrated circuit. The latch asserts a first signal in response to sensing the occurrence of the voltage transient at the input pad. A transient protection circuit is coupled to the input pad for coupling the input pad to ground in response to the latch asserting the first signal such that current associated with the voltage transient is shunted to ground. A circuit is coupled to the latch for preventing the latch from asserting the first signal in response to the occurrence of the voltage transient if a predetermined condition exists. According to a present embodiment, the circuit is a timer that disables the latch in response to a supply output voltage VCC exceeding a predetermined level.

Abstract translation: 用于防止由于在集成电路外部引入的电压瞬变而导致对集成电路的电路的损坏的装置。 根据一个实施例，电压瞬变是由于静电放电（ESD）引起的。 该装置包括用于耦合到集成电路的输入焊盘的锁存器。 响应于感测输入焊盘处的电压瞬变的发生，锁存器断言第一信号。 瞬态保护电路耦合到输入焊盘，用于响应于锁存器将输入焊盘耦合到地来确定第一信号，使得与电压瞬变相关联的电流被分流到地。 如果存在预定条件，则电路耦合到锁存器，用于防止锁存器响应于电压瞬变的发生来确定第一信号。 根据本实施例，电路是响应于超过预定电平的电源输出电压VCC而禁用锁存器的定时器。

公开(公告)号：US20130258781A1

公开(公告)日：2013-10-03

申请号：US13438331

申请日：2012-04-03

Applicant: Akira Goda ,  Yijie Zhao ,  Krishna Parat

Inventor： Akira Goda ,  Yijie Zhao ,  Krishna Parat

IPC: G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

Abstract: Devices, systems and methods of biasing in memory devices facilitate memory device programming and/or erase operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source where the data line and the source are biased to substantially the same potential during a programming and/or erase operation performed on one or more of the strings of memory cells.

Abstract translation: 存储器件中的偏置的装置，系统和方法促进存储器件编程和/或擦除操作。 在至少一个实施例中，包括所选择的存储器单元和第二存储单元串的存储器单元的第一串被耦合到公共数据线和公共源，其中数据线和源被偏置到基本上相同的电位 对一个或多个存储器单元串执行编程和/或擦除操作。

公开(公告)号：US08498159B2

公开(公告)日：2013-07-30

申请号：US13465328

申请日：2012-05-07

Applicant: Akira Goda ,  Tomoharu Tanaka ,  Krishna Parat ,  Prashant Damle ,  Shafqat Ahmed

Inventor： Akira Goda ,  Tomoharu Tanaka ,  Krishna Parat ,  Prashant Damle ,  Shafqat Ahmed

IPC: G11C11/34

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.

Abstract translation: 提供了用于编程存储器件的方法，被配置为执行所公开的编程方法的存储器件，以及具有被配置为执行所公开的编程方法的存储器件的存储器系统。 根据至少一种这样的方法，在对存储器件执行的编程操作期间，各自具有存储器单元串的多个独立的半导体阱区被独立地偏置。 响应于独立的井偏置方法，在编程操作期间可以实现减少的电荷泄漏。

公开(公告)号：US08331160B2

公开(公告)日：2012-12-11

申请号：US13193192

申请日：2011-07-28

Applicant: Prashant S. Damle ,  Krishna Parat ,  Alessandro Torsi ,  Carlo Musilli ,  Kalpana Vakati ,  Akira Goda

Inventor： Prashant S. Damle ,  Krishna Parat ,  Alessandro Torsi ,  Carlo Musilli ,  Kalpana Vakati ,  Akira Goda

IPC: G11C11/34

CPC classification number: G11C16/3404 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/32

Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.

Abstract translation: 一些实施例包括具有模块和存储器单元的方法和装置。 该模块被配置为在编程操作期间减少存储器单元的源极和漏极中的电子量。

公开(公告)号：US20120218824A1

公开(公告)日：2012-08-30

申请号：US13465328

申请日：2012-05-07

Applicant: Akira Goda ,  Tomoharu Tanaka ,  Krishna Parat ,  Prashant Damle ,  Shafqat Ahmed

Inventor： Akira Goda ,  Tomoharu Tanaka ,  Krishna Parat ,  Prashant Damle ,  Shafqat Ahmed

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.

Abstract translation: 提供了用于编程存储器件的方法，被配置为执行所公开的编程方法的存储器件，以及具有被配置为执行所公开的编程方法的存储器件的存储器系统。 根据至少一种这样的方法，在对存储器件执行的编程操作期间，各自具有存储器单元串的多个独立的半导体阱区被独立地偏置。 响应于独立的井偏置方法，在编程操作期间可以实现减少的电荷泄漏。