公开(公告)号：US20170091022A1

公开(公告)日：2017-03-30

申请号：US14866291

申请日：2015-09-25

申请人： JAWAD B. KHAN ,  ANAND S. RAMALINGAM ,  PRANAV KALAVADE

发明人： JAWAD B. KHAN ,  ANAND S. RAMALINGAM ,  PRANAV KALAVADE

IPC分类号： G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC分类号： G06F11/1068 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0688 ,  G06F11/108 ,  G11C29/52 ,  G11C2029/0411

摘要： Examples may include techniques to recover data from a solid state drive (SSD) using exclusive OR (XOR) parity information. Data saved to non-volatile types of block-erasable memory such as NAND memory included in the SSD may be recovered via use of XOR parity information saved to types of write-in-place memory such as a 3-dimensional cross-point memory also included in the SSD.

公开(公告)号：US20150179267A1

公开(公告)日：2015-06-25

申请号：US14139219

申请日：2013-12-23

申请人： Charan Srinivasan ,  Pranav Kalavade ,  Shyam Sunder Raghunathan ,  Krishna K. Parat

发明人： Charan Srinivasan ,  Pranav Kalavade ,  Shyam Sunder Raghunathan ,  Krishna K. Parat

IPC分类号： G11C16/10 ,  G11C16/28

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/28 ,  G11C16/3454

摘要： Embodiments of methods and systems disclosed herein provide a NAND cell programming technique that results in a substantially reduced Tprog to complete a programming operation. In particular, embodiments of the subject matter disclosed herein utilize two Vpgm programming pulses during each programming iteration, or loop. One of the two programming pulses corresponds to a conventional programming Vpgm pulse and the second pulse comprises a programming pulse that having a greater Vpgm that is greater than the conventional programming Vpgm so that the slow cells are programmed to PV in fewer pulses (iterations), thereby effectively simultaneously programming and verifying cells having different programming speeds.

摘要翻译： 本文公开的方法和系统的实施例提供NAND单元编程技术，其导致基本上减少的T程序以完成编程操作。 特别地，本文公开的主题的实施例在每个编程迭代期间利用两个Vpgm编程脉冲或循环。 两个编程脉冲之一对应于常规编程Vpgm脉冲，第二脉冲包括具有比常规编程Vpgm更大的Vpgm的编程脉冲，使得慢单元以更少的脉冲（迭代）被编程为PV， 从而有效地同时编程和验证具有不同编程速度的单元。

公开(公告)号：US20140380108A1

公开(公告)日：2014-12-25

申请号：US13977011

申请日：2012-03-29

申请人： Matthew Goldman ,  Krishna K. Parat ,  Pranav Kalavade ,  Nathan R. Franklin ,  Mark Helm

发明人： Matthew Goldman ,  Krishna K. Parat ,  Pranav Kalavade ,  Nathan R. Franklin ,  Mark Helm

IPC分类号： G11C29/50 ,  G06F11/10

CPC分类号： G11C29/50004 ,  G06F11/1048 ,  G06F11/1068 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/34 ,  G11C2029/0411 ,  G11C2029/5004

摘要： An apparatus may include a processor circuit a processor circuit to retrieve data from a non-volatile memory, and a multistrobe read module operable on the processor circuit to set a read operation to read a memory cell over a multiplicity of sense operations, where each sense operation is performed under a different sense condition. The multistrobe read module may be further operable to schedule a new sense operation to succeed a prior sense operation of the multiplicity of sense operations without recharge of the wordline when a value of one or more read condition is within a preset range. Other embodiments are disclosed and claimed.

摘要翻译： 一种装置可以包括处理器电路，用于从非易失性存储器检索数据，以及多处理器读取模块，其可在所述处理器电路上操作以设置读取操作以在多种感测操作上读取存储器单元， 在不同的感测条件下进行操作。 当一个或多个读取条件的值处于预设范围内时，该多画面读取模块还可以进一步操作，以调度新的感测操作，从而在许多感测操作的先前感测操作中继续进行，而不对字线进行再充电。 公开和要求保护其他实施例。

公开(公告)号：US08411508B2

公开(公告)日：2013-04-02

申请号：US12573579

申请日：2009-10-05

申请人： Pranav Kalavade ,  Krishna K. Parat ,  Paul D. Ruby

发明人： Pranav Kalavade ,  Krishna K. Parat ,  Paul D. Ruby

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Apparatus, methods, and systems are disclosed, including those to improve program voltage distribution width using automatic selective slow program convergence (ASSPC). One such method may include determining whether a threshold voltage (Vt) associated with a memory cell has reached a particular pre-program verify voltage. In response to the determination, a voltage applied to a bit-line coupled to the memory cell may be automatically incremented at least twice as the program voltage is increased, until the cell is properly programmed. Additional embodiments are also described.

摘要翻译： 公开了装置，方法和系统，包括使用自动选择性慢程序融合（ASSPC）来提高编程电压分配宽度的装置，方法和系统。 一种这样的方法可以包括确定与存储器单元相关联的阈值电压（Vt）是否已经达到特定的预编程验证电压。 响应于该确定，施加到耦合到存储器单元的位线的电压可以自动递增至少两倍于编程电压增加，直到单元被适当地编程为止。 还描述了另外的实施例。

公开(公告)号：US08248862B2

公开(公告)日：2012-08-21

申请号：US12636896

申请日：2009-12-14

申请人： Ercole Rosario Di Iorio ,  Giulio Giuseppe Marotta ,  Marco Domenico Tiburzi ,  Pranav Kalavade

发明人： Ercole Rosario Di Iorio ,  Giulio Giuseppe Marotta ,  Marco Domenico Tiburzi ,  Pranav Kalavade

IPC分类号： G11C7/00

CPC分类号： G11C5/145 ,  G11C11/5628 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C16/0483 ,  G11C16/30

摘要： The threshold voltage range of a multilevel memory cell may be increased without using a negative voltage pump. In one embodiment, an added positive voltage may be applied to the source of the selected cell. A boost voltage may be applied to the output of a sense amplifier. Non-ideal characteristics of a buffer that supplies the voltage to the selected cell may be compensated for in some embodiments.

摘要翻译： 可以在不使用负电压泵的情况下增加多电平存储器单元的阈值电压范围。 在一个实施例中，可以向所选择的单元的源施加附加的正电压。 升压电压可以被施加到读出放大器的输出。 在一些实施例中，可以补偿向所选择的单元提供电压的缓冲器的非理想特性。

公开(公告)号：US08072022B2

公开(公告)日：2011-12-06

申请号：US12317535

申请日：2008-12-24

申请人： Pranav Kalavade ,  Krishna Parat ,  Ervin Hill ,  Kiran Pangal

发明人： Pranav Kalavade ,  Krishna Parat ,  Ervin Hill ,  Kiran Pangal

IPC分类号： H01L29/423 ,  H01L29/739

CPC分类号： G11C16/0416 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

摘要： Embodiments of an apparatus and methods for providing improved flash memory cell characteristics are generally described herein. Other embodiments may be described and claimed.

摘要翻译： 本文通常描述用于提供改进的闪速存储器单元特性的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20140115231A1

公开(公告)日：2014-04-24

申请号：US13658449

申请日：2012-10-23

申请人： Ravi H. Motwani ,  Pranav Kalavade

发明人： Ravi H. Motwani ,  Pranav Kalavade

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F11/1072 ,  G06F12/02

摘要： Apparatus, systems, and methods manage NAND memory are described. In one embodiment, an apparatus comprises a memory controller logic to apply a binary parity check code to a binary string and convert the binary string to a ternary string. Other embodiments are also disclosed and claimed.

摘要翻译： 描述管理NAND存储器的装置，系统和方法。 在一个实施例中，一种装置包括存储器控制器逻辑，用于将二进制奇偶校验码应用于二进制串并将二进制串转换为三进制串。 还公开并要求保护其他实施例。

公开(公告)号：US08681562B2

公开(公告)日：2014-03-25

申请号：US13051599

申请日：2011-03-18

申请人： Pranav Kalavade ,  Akira Goda ,  Tommaso Vali ,  Violante Moschiano

发明人： Pranav Kalavade ,  Akira Goda ,  Tommaso Vali ,  Violante Moschiano

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459

摘要： Apparatus and methods for adjusting programming for upper pages of memories are disclosed. In at least one embodiment, a threshold voltage distribution upper limit is determined after a single programming pulse for lower page programming, and upper page programming start voltages are adjusted based on the determined upper limit of the threshold voltage distribution.

摘要翻译： 公开了用于调整存储器上部页面编程的装置和方法。 在至少一个实施例中，在用于较低页编程的单个编程脉冲之后确定阈值电压分布上限，并且基于所确定的阈值电压分布的上限来调整上页编程开始电压。

公开(公告)号：US20130322170A1

公开(公告)日：2013-12-05

申请号：US13486767

申请日：2012-06-01

申请人： Matthew Goldman ,  Pranav Kalavade ,  Uday Chandrasekhar ,  Mark A. Helm

发明人： Matthew Goldman ,  Pranav Kalavade ,  Uday Chandrasekhar ,  Mark A. Helm

IPC分类号： G11C16/28 ,  G11C16/04

CPC分类号： G11C16/28 ,  G06F12/0875 ,  G06F2212/452 ,  G11C16/04 ,  G11C16/26 ,  G11C16/3427

摘要： This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.

公开(公告)号：US08542531B2

公开(公告)日：2013-09-24

申请号：US12829729

申请日：2010-07-02

申请人： Nathan R. Franklin ,  Pranav Kalavade

发明人： Nathan R. Franklin ,  Pranav Kalavade

IPC分类号： G11C11/34

CPC分类号： G11C16/3454 ,  G11C11/10 ,  G11C11/5642

摘要： Methods for accelerating charge equilibrium in a non-volatile memory device using floating gate memory cells are disclosed. Memory devices and storage systems using charge equilibrium acceleration are also disclosed. In one such method, a programming pulse is applied to the word line to change an amount of charge stored on the floating gate of the memory cells being programmed. A reverse field pulse is then applied to the memory cell using only voltages greater than or equal to about 0 volts. The reverse field pulse accelerates charge equilibrium by moving any electrons trapped in the insulating oxide layers to a stable location so that the threshold voltage is stabilized. After the reverse field pulse, a program verify operation is performed and additional programming pulses and reverse field pulses are applied as needed to properly program the memory cell.

摘要翻译： 公开了使用浮动栅极存储器单元在非易失性存储器件中加速电荷平衡的方法。 还公开了使用充电平衡加速度的存储器件和存储系统。 在一种这样的方法中，将编程脉冲施加到字线以改变存储在正被编程的存储器单元的浮动栅极上的电荷量。 然后仅使用大于或等于约0伏的电压将反向场脉冲施加到存储器单元。 反向场脉冲通过将捕获在绝缘氧化物层中的任何电子移动到稳定位置来加速电荷平衡，使得阈值电压稳定。 在反向场脉冲之后，执行程序验证操作，并且根据需要施加附加的编程脉冲和反向场脉冲以正确编程存储单元。