Lightweight highly available infrastructure to trace program execution
    11.
    发明授权
    Lightweight highly available infrastructure to trace program execution 有权
    轻量级高可用性的基础架构跟踪程序执行

    公开(公告)号:US07770154B2

    公开(公告)日:2010-08-03

    申请号:US11173675

    申请日:2005-07-01

    CPC classification number: G06F11/3471 G06F11/3636

    Abstract: A portable tracing utility provides trace configuration, trace instrumentation and trace management functionality for single or multithreaded programs. Through various application programming interfaces (“APIs”) of the tracing utility, a client may control tracing behavior to setup in-memory data structures for storing trace records that record the program's history of execution or to alter the granularity of execution history being traced. The trace behavior can be modified during the life of a program by using the APIs, either dynamically when the program assumes certain states, or through remote procedure calls issued by, for example, an external interface. Programs are instrumented with these APIs to record the history of execution, which during execution of the program is stored in circular in-memory buffers.

    Abstract translation: 便携式跟踪实用程序为单个或多线程程序提供跟踪配置,跟踪检测和跟踪管理功能。 通过跟踪实用程序的各种应用程序编程接口(“API”),客户端可以控制跟踪行为来设置内存中的数据结构,以存储跟踪记录,记录程序的执行历史或更改正在跟踪的执行历史的粒度。 跟踪行为可以在程序生命周期内通过使用API​​进行修改,或者通过例如外部接口发出的远程过程调用,动态执行某些状态。 使用这些API对程序进行测试,以记录执行历史,在执行程序期间将其存储在循环内存缓冲区中。

    Backing up Data from Backup Target to Backup Facility
    13.
    发明申请
    Backing up Data from Backup Target to Backup Facility 有权
    将数据从备份目标备份到备份设备

    公开(公告)号:US20090292888A1

    公开(公告)日:2009-11-26

    申请号:US12125904

    申请日:2008-05-22

    CPC classification number: G06F11/1464 G06F11/1461

    Abstract: Aspects of the subject matter described herein relate to backup up data. In aspects, a backup target determines a degree to which a data set included on the backup target is not backed up on a backup facility. The degree can represent more than just that the data set is completely backed up or is not backed up at all. If the degree satisfies a condition, the backup target utilizes information derived from a backup history of one or more attempted or successfully completed backup sessions between the backup target and the backup facility to determine whether to provide a notification regarding backup state. The backup target also may send the degree and other backup information to a backup facility which may use this information in determining a backup scheme to employ with the backup target.

    Abstract translation: 本文描述的主题的方面涉及备份数据。 在一个方面,备份目标确定在备份设备上不备份备份目标上包括的数据集的程度。 该程度不仅可以表示数据集完全备份或根本不备份。 如果程度满足条件,则备份目标利用从备份目标和备份设施之间的一个或多个尝试或成功完成的备份会话的备份历史导出的信息来确定是否提供关于备份状态的通知。 备份目标还可以将度数和其他备份信息发送到备份设备,备份设备可以使用该信息来确定与备份目标一起使用的备份方案。

    System and method for monitoring clock signal in an integrated circuit
    14.
    发明授权
    System and method for monitoring clock signal in an integrated circuit 有权
    用于监控集成电路中的时钟信号的系统和方法

    公开(公告)号:US07498848B2

    公开(公告)日:2009-03-03

    申请号:US11851380

    申请日:2007-09-06

    CPC classification number: H03K5/19 G01R31/31725 G01R31/31727 H03K5/26

    Abstract: A clock monitor system for monitoring an input clock signal in an integrated circuit (IC) includes a clock failure detection circuit and a delay circuit. The clock failure detection circuit generates a control signal based on the input clock signal. The delay circuit is connected to the clock failure detection circuit and provides a clock status signal based on the control signal. The clock status signal indicates whether the input clock signal is operating correctly. The delay circuit provides the clock status signal to the IC after a predetermined number of input clock cycles.

    Abstract translation: 用于监视集成电路(IC)中的输入时钟信号的时钟监视器系统包括时钟故障检测电路和延迟电路。 时钟故障检测电路基于输入时钟信号产生控制信号。 延迟电路连接到时钟故障检测电路,并根据控制信号提供时钟状态信号。 时钟状态信号指示输入时钟信号是否正常工作。 延迟电路在预定数量的输入时钟周期之后向IC提供时钟状态信号。

    Infrastructure for verifying configuration and health of a multi-node computer system
    15.
    发明授权
    Infrastructure for verifying configuration and health of a multi-node computer system 有权
    用于验证多节点计算机系统的配置和运行状况的基础结构

    公开(公告)号:US07434041B2

    公开(公告)日:2008-10-07

    申请号:US11209515

    申请日:2005-08-22

    CPC classification number: G06F9/44589

    Abstract: A verification infrastructure uses a verification tool with a user interface with which a user may interact to verify an application and/or its platform. The user may enter the same set of commands to verify instances of the application on different platforms. Furthermore, the verification tool is data driven in a way that allows the verification tool to be easily extended to new platforms. Finally, details of a particular configuration are stored persistently and are used by the verification tool to perform verification. Thus, much of the complex work of acquiring knowledge about the configuration and applying the knowledge to the results of various checks made for verification is performed by the verification tool and not a human user.

    Abstract translation: 验证基础设施使用具有用户界面的验证工具,用户可以与用户界面进行交互以验证应用程序和/或其平台。 用户可以输入相同的命令集来验证不同平台上应用程序的实例。 此外,验证工具是以允许验证工具轻松扩展到新平台的方式进行数据驱动的。 最后,特定配置的细节被永久存储,由验证工具用来执行验证。 因此,获取关于配置的知识和将知识应用于用于验证的各种检查的结果的许多复杂工作由验证工具而不是人类用户来执行。

    SYSTEM AND METHOD FOR MONITORING CLOCK SIGNAL IN AN INTEGRATED CIRCUIT
    16.
    发明申请
    SYSTEM AND METHOD FOR MONITORING CLOCK SIGNAL IN AN INTEGRATED CIRCUIT 有权
    用于监控集成电路中的时钟信号的系统和方法

    公开(公告)号:US20080079463A1

    公开(公告)日:2008-04-03

    申请号:US11851380

    申请日:2007-09-06

    CPC classification number: H03K5/19 G01R31/31725 G01R31/31727 H03K5/26

    Abstract: A clock monitor system for monitoring an input clock signal in an integrated circuit (IC) includes a clock failure detection circuit and a delay circuit. The clock failure detection circuit generates a control signal based on the input clock signal. The delay circuit is connected to the clock failure detection circuit and provides a clock status signal based on the control signal. The clock status signal indicates whether the input clock signal is operating correctly. The delay circuit provides the clock status signal to the IC after a predetermined number of input clock cycles.

    Abstract translation: 用于监视集成电路(IC)中的输入时钟信号的时钟监视器系统包括时钟故障检测电路和延迟电路。 时钟故障检测电路基于输入时钟信号产生控制信号。 延迟电路连接到时钟故障检测电路,并根据控制信号提供时钟状态信号。 时钟状态信号指示输入时钟信号是否正常工作。 延迟电路在预定数量的输入时钟周期之后向IC提供时钟状态信号。

    Detecting a state change in a lock structure to validate a potential deadlock
    19.
    发明授权
    Detecting a state change in a lock structure to validate a potential deadlock 有权
    检测锁结构中的状态变化以验证潜在的僵局

    公开(公告)号:US06304938B1

    公开(公告)日:2001-10-16

    申请号:US09256330

    申请日:1999-02-23

    CPC classification number: G06F9/524

    Abstract: A mechanism for deadlock validation is provided. A potential deadlock is validated by detecting whether a state change has occurred in a member of a set of lock structures that correspond to entities and resources involved in a potential deadlock. The state change detected should have occurred after the state of the lock structures is captured during, for example, the generation of a wait-for graph. For purposes of illustration, potential deadlocks are identified by generating a wait-for graph and detecting cycles in the wait-for graph. While generating wait-for graphs, lock structures are accessed to determine whether a vertex in the wait-for graph should be generated, and the place of the vertex in the wait-for graph. After accessing a particular lock structure for this purpose, the lock structure's state is captured. If the state of the lock structure changes after the state is captured, then any cycle that includes the lock structure may not be valid, and a potential deadlock identified by the cycle is deemed a false deadlock.

    Abstract translation: 提供了一种用于死锁验证的机制。 通过检测在一组锁定结构的成员中是否发生了与潜在的死锁中涉及的实体和资源相对应的状态改变来验证潜在的死锁。 检测到的状态变化应该在例如生成等待图之前捕获锁结构的状态之后发生。 为了说明的目的,通过在等待图中生成等待图和检测周期来识别潜在的死锁。 在生成等待图时,可以访问锁结构以确定等待图中的顶点是否应生成,等待图中的顶点位置。 在为此目的访问特定的锁定结构之后,捕获锁定结构的状态。 如果锁定结构的状态在状态被捕获之后发生变化,则包含锁定结构的任何周期都可能不是有效的,并且由循环识别的潜在的死锁被认为是假死锁。

    Method of fast gain control in WDM optical networks
    20.
    发明授权
    Method of fast gain control in WDM optical networks 失效
    WDM光网络快速增益控制方法

    公开(公告)号:US5900968A

    公开(公告)日:1999-05-04

    申请号:US728629

    申请日:1996-10-10

    CPC classification number: H04B10/296 H04B10/2912 H04B10/2935 H04J14/0221

    Abstract: In a WDM network employing a plurality of optical amplifiers in at least one optical fiber link, a system and method for dynamically controlling gain in accordance with the collective behavior of the amplifier chain. According to the present invention, the required response time of dynamic gain control is selected substantially inversely relative to the number of amplifiers in the communication path. Illustratively, in a large-scale optical network (with signal channel paths traversing say, a hundred optical amplifiers), the response time of gain control in accordance with the present invention may be on the order of 5 .mu.s or even less.

    Abstract translation: 在至少一个光纤链路中使用多个光放大器的WDM网络中,根据放大器链的集体行为来动态地控制增益的系统和方法。 根据本发明,动态增益控制的所需响应时间相对于通信路径中的放大器的数量基本上相反地选择。 说明性地,在大规模光网络(具有通过数百个光放大器的信道通道)中,根据本发明的增益控制的响应时间可以在5μs甚至更小的数量级。

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