公开(公告)号：US20090070657A1

公开(公告)日：2009-03-12

申请号：US12264959

申请日：2008-11-05

Applicant: Simon Litsyn ,  Idan Alrod ,  Eran Sharon ,  Mark Murin ,  Menahem Lasser

Inventor： Simon Litsyn ,  Idan Alrod ,  Eran Sharon ,  Mark Murin ,  Menahem Lasser

IPC: H03M13/05 ,  G06F11/10

CPC classification number: G06F11/1072

Abstract: A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods.

Abstract translation: 多个逻辑页面与相应的ECC位一起存储在MBC闪速存储器中，其中至少一个MBC单元存储来自多于一个逻辑页面的位，并且至少一个ECC位应用于两个或多个 逻辑页面。 当从存储器中读取页面时，读取的数据位使用读取的ECC位进行校正。 或者，针对两个或多个逻辑页面计算联合的，系统的或非系统的ECC码字，并且存储该代码字而不是那些逻辑页面。 当读取联合码字时，从读取的码字中恢复逻辑比特。 本发明的范围还包括对应的存储器件，这种存储器件的控制器，以及用于实现该方法的具有计算机可读代码的计算机可读存储介质。

公开(公告)号：US20080259684A1

公开(公告)日：2008-10-23

申请号：US11806111

申请日：2007-05-30

Applicant: Mark Shlick ,  Mark Murin

Inventor： Mark Shlick ,  Mark Murin

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5621 ,  G11C2211/5648

Abstract: When a memory device receives two or more pluralities of bits from a host to store in a nonvolatile memory, the device first stores the bits in a volatile memory. Then, in storing the bits in the nonvolatile memory, the device raises the threshold voltages of some cells of the volatile memory to values above a verify voltage. While those threshold voltages remain substantially at those levels, the device raises the threshold voltages of other cells of the volatile memory to values below the verify voltage. In the end, every cell stores one or more bits from each plurality of bits. Preferably, all the cells share a common wordline. A data storage device operates similarly with respect to storing pluralities of bits generated by an application running on the system.

Abstract translation: 当存储器装置从主机接收两个或多个多个比特以存储在非易失性存储器中时，该装置首先将该比特存储在易失性存储器中。 然后，在将位存储在非易失性存储器中时，该器件将易失性存储器的一些单元的阈值电压提高到高于验证电压的值。 当这些阈值电压基本保持在这些电平时，器件将易失性存储器的其他单元的阈值电压升高到低于验证电压的值。 最后，每个单元存储来自每个位的一个或多个位。 优选地，所有细胞共享公共字线。 数据存储设备的操作类似地存储由在系统上运行的应用程序生成的多个位。

公开(公告)号：US20080002465A1

公开(公告)日：2008-01-03

申请号：US11785302

申请日：2007-04-17

Applicant: Mark Murin

Inventor： Mark Murin

IPC: G11C11/34

CPC classification number: G11C8/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5634

Abstract: A multi-bit-per-cell flash memory device supports a command such that each invocation of the command by the device's host changes respective values of one or more types of reference voltage (e.g., all read reference voltages and/or all program verify reference voltages) of the device to respective new values.

Abstract translation: 多单元闪存设备支持命令，使得设备主机对命令的每次调用改变一种或多种类型的参考电压的相应值（例如，所有读取的参考电压和/或所有程序验证参考 电压）到相应的新值。

公开(公告)号：US20070061502A1

公开(公告)日：2007-03-15

申请号：US11318906

申请日：2005-12-28

Applicant: Menahem Lasser ,  Mark Murin ,  Arik Eyal

Inventor： Menahem Lasser ,  Mark Murin ,  Arik Eyal

IPC: G06F12/00

CPC classification number: G11C11/5621 ,  G06F12/0246 ,  G06F12/0866 ,  G06F2212/2022 ,  G06F2212/7211 ,  G11C16/349 ,  G11C16/3495 ,  G11C2211/5641

Abstract: A flash memory storage system includes a memory array containing a plurality of memory cells and a controller for controlling the flash memory array. The controller dedicates a first group of memory cells to operate with a first number of bits per cell and a second, separate group of memory cells to operate with a second number of bits per cell. A mechanism is provided to apply wear leveling techniques separately to the two groups of cells to evenly wear out the memory cells.

Abstract translation: 闪速存储器存储系统包括包含多个存储器单元的存储器阵列和用于控制闪速存储器阵列的控制器。 控制器专用于第一组存储器单元以每个单元的第一个位数和第二个单独的存储器单元组以每个单元的第二个位数来操作。 提供了一种机制来将磨损均衡技术分别应用于两组细胞以均匀地磨损存储单元。

公开(公告)号：US08069380B2

公开(公告)日：2011-11-29

申请号：US12755519

申请日：2010-04-07

Applicant: Mark Murin ,  Menahem Lasser ,  Avraham Meir

Inventor： Mark Murin ,  Menahem Lasser ,  Avraham Meir

IPC: G11C29/00 ,  G06F11/00

CPC classification number: G11C29/48 ,  G01R31/318513 ,  G11C29/1201 ,  G11C2029/0401 ,  G11C2029/1208

Abstract: A flash memory device includes a flash memory residing on at least one flash memory die. The flash memory device also includes a flash controller residing on a flash controller die that is separate from the at least one flash memory die. The flash memory and the flash controller reside within, reside on, or are attached to a common housing. The flash controller is configured to execute at least one test program to test at least one flash memory die.

Abstract translation: 闪存设备包括驻留在至少一个闪存存储器模块上的闪存。 闪存设备还包括驻留在闪存控制器管芯上的与至少一个闪存管芯分离的闪存控制器。 闪存和闪存控制器驻留在，驻留在或连接到公共外壳。 闪存控制器被配置为执行至少一个测试程序来测试至少一个闪存芯片。

公开(公告)号：US08020060B2

公开(公告)日：2011-09-13

申请号：US11623328

申请日：2007-01-16

Applicant: Mark Murin

Inventor： Mark Murin

IPC: H04L1/00 ,  G08C25/00 ,  H03M13/00 ,  G06F11/30

CPC classification number: G11C11/5621 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5628 ,  G11C16/0483 ,  G11C29/00

Abstract: A method of storing data includes storing a first portion of data in bit positions of a non-volatile memory having a first probability of error; storing a second portion of the data in bit positions of the non-volatile memory having a second probability of error, wherein the second probability of error is lower than the first probability of error; storing error correction parity bits with the data; and applying an error correction scheme to read data using the error correction parity bits, wherein at least one bit of the first portion is checked for correction before any bit of the second portion is checked for correction. The error correction scheme is stopped before checking for correcting of all the data.

Abstract translation: 存储数据的方法包括：将具有第一误差概率的非易失性存储器的位位置中的数据的第一部分存储; 将所述数据的第二部分存储在具有第二误差概率的所述非易失性存储器的比特位置中，其中所述第二误差概率低于所述第一误差概率; 存储纠错奇偶校验位与数据; 以及使用纠错奇偶校验位来应用纠错方案来读取数据，其中在检查所述第二部分的任何位之前检查所述第一部分的至少一位以进行校正。 在检查所有数据的校正之前，停止纠错方案。

公开(公告)号：US20110013450A1

公开(公告)日：2011-01-20

申请号：US12890267

申请日：2010-09-24

Applicant: Mark Murin ,  Menahem Lasser

Inventor： Mark Murin ,  Menahem Lasser

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

Abstract: A method in which non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non-volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, performance can be optimized, including addressing changes in threshold voltage which are caused by program disturb. In one approach, different sets of storage elements in a memory device are programmed with random test data. A threshold voltage distribution is determined for the different sets of storage elements. A set of voltages is determined based on the threshold voltage distribution, and stored in a non-volatile storage location for subsequent use in accessing the different sets of storage elements. The set of voltages may be determined at the time of manufacture for subsequent use in accessing data by the end user.

Abstract translation: 使用针对设备定制的电压和/或设备的部分（诸如非易失性存储元件的块或字线）访问非易失性存储器件的方法。 访问可以包括编程，验证或阅读。 通过定制电压，可以优化性能，包括寻址由程序干扰引起的阈值电压变化。 在一种方法中，存储器件中的不同存储元件组被编程为随机测试数据。 确定不同组的存储元件的阈值电压分布。 一组电压基于阈值电压分布来确定，并且存储在非易失性存储位置中，用于随后用于访问不同组的存储元件。 可以在制造时确定该组电压以供随后在最终用户访问数据中使用。

公开(公告)号：US07808819B2

公开(公告)日：2010-10-05

申请号：US12111729

申请日：2008-04-29

Applicant: Mark Murin ,  Menahem Lasser

Inventor： Mark Murin ,  Menahem Lasser

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5621

Abstract: A method in which non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non-volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, performance can be optimized, including addressing changes in threshold voltage which are caused by program disturb. In one approach, different sets of storage elements in a memory device are programmed with random test data. A threshold voltage distribution is determined for the different sets of storage elements. A set of voltages is determined based on the threshold voltage distribution, and stored in a non-volatile storage location for subsequent use in accessing the different sets of storage elements. The set of voltages may be determined at the time of manufacture for subsequent use in accessing data by the end user.

Abstract translation: 使用针对设备定制的电压和/或设备的诸如非易失性存储元件的块或字线的部分来访问非易失性存储器件的方法。 访问可以包括编程，验证或阅读。 通过定制电压，可以优化性能，包括寻址由程序干扰引起的阈值电压变化。 在一种方法中，存储器件中的不同存储元件组被编程为随机测试数据。 确定不同组的存储元件的阈值电压分布。 一组电压基于阈值电压分布来确定，并且存储在非易失性存储位置中，用于随后用于访问不同组的存储元件。 可以在制造时确定该组电压以供随后在最终用户访问数据中使用。

公开(公告)号：US07752382B2

公开(公告)日：2010-07-06

申请号：US11318906

申请日：2005-12-28

Applicant: Menahem Lasser ,  Mark Murin ,  Arik Eyal

Inventor： Menahem Lasser ,  Mark Murin ,  Arik Eyal

IPC: G06F13/14

CPC classification number: G11C11/5621 ,  G06F12/0246 ,  G06F12/0866 ,  G06F2212/2022 ,  G06F2212/7211 ,  G11C16/349 ,  G11C16/3495 ,  G11C2211/5641

Abstract: A flash memory storage system includes a memory array containing a plurality of memory cells and a controller for controlling the flash memory array. The controller dedicates a first group of memory cells to operate with a first number of bits per cell and a second, separate group of memory cells to operate with a second number of bits per cell. A mechanism is provided to apply wear leveling techniques separately to the two groups of cells to evenly wear out the memory cells.

Abstract translation: 闪速存储器存储系统包括包含多个存储器单元的存储器阵列和用于控制闪速存储器阵列的控制器。 控制器专用于第一组存储器单元以每个单元的第一个位数和第二个单独的存储器单元组以每个单元的第二个位数来操作。 提供了一种机制来将磨损均衡技术分别应用于两组细胞以均匀地磨损存储单元。

公开(公告)号：US20090327841A1

公开(公告)日：2009-12-31

申请号：US12401634

申请日：2009-03-11

Applicant: Simon LITSYN ,  Idan Alrod ,  Eran Sharon ,  Mark Murin ,  Menahem Lasser

Inventor： Simon LITSYN ,  Idan Alrod ,  Eran Sharon ,  Mark Murin ,  Menahem Lasser

IPC: H03M13/03 ,  H03M13/09 ,  G06F11/10 ,  G06F11/07

CPC classification number: H03M13/458 ,  G06F11/1012 ,  G06F11/1024 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C2029/0409 ,  H03M13/45

Abstract: Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

Abstract translation: 根据系统或非系统ECC存储在多比特单元存储器的单元中的数据根据​​估计的概率被读取和校正（系统ECC）或恢复（非系统ECC） 更多的读取位是错误的。 在本发明的一种方法中，估计是先验的。 在本发明的另一种方法中，估计仅基于包括读位的重要性或位页的读位的方面。 在本发明的第三种方法中，估计仅基于读位的值。 并不是所有的估计是相等的。