公开(公告)号：US07772406B2

公开(公告)日：2010-08-10

申请号：US12084316

申请日：2006-10-30

申请人： Masao Morimoto ,  Atsushi Yamakawa

发明人： Masao Morimoto ,  Atsushi Yamakawa

IPC分类号： A61K31/40 ,  C07D207/12

CPC分类号： C07D207/12

摘要： Provided are: a process for production of a benzyloxypyrrolidine derivative in high yield and safety, and a process for production of a hydrochloride powder of a benzyloxypyrrolidine derivative in high yield and safety; the process for production of a benzyloxypyrrolidine derivative expressed by the general formula (2) [Chemical formula 2], in reacting a pyrrolidinol derivative represented by the general formula (1) [Chemical formula 1] with a benzyl halide derivative in the presence of an alkali metal hydroxide, wherein the reaction is carried out in either of the following conditions A or B; condition A: an aprotic polar solvent, and condition B: an aliphatic ether solvent containing a phase transfer catalyst:

摘要翻译： 本发明提供以高产率和安全的方式生产苄氧基吡咯烷衍生物的方法，以及高生产率和安全性生产苄氧基吡咯烷衍生物的盐酸盐粉末的方法; 在通式（2）[化学式2]表示的苄氧基吡咯烷衍生物的制备方法中，在通式（1）[化学式1]表示的吡咯烷醇衍生物与苄基卤衍生物在 碱金属氢氧化物，其中反应在以下任一条件A或B中进行; 条件A：非质子极性溶剂，条件B：含有相转移催化剂的脂族醚溶剂：

公开(公告)号：US20100177580A1

公开(公告)日：2010-07-15

申请号：US12687339

申请日：2010-01-14

申请人： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki

发明人： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki

IPC分类号： G11C7/00 ,  G11C7/02

CPC分类号： G11C11/413 ,  G11C7/08 ,  G11C7/22 ,  G11C7/227

摘要： Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers.

摘要翻译： 即使使用复制位线的存储器的存储器容量更高，读出放大器使能信号的产生定时的波动也减小。 半导体集成电路器件包括多个字线，多个位线，多个普通存储器单元，访问控制电路，多个读出放大器，第一和第二复制位线，第一和第二复制 存储单元，以及第一和第二逻辑电路。 第一和第二复制存储器单元分别连接到第一和第二复制位线; 第一和第二逻辑电路的输入分别连接到第一和第二复制位线; 从第二逻辑电路的输出产生读出放大器使能信号; 并且该信号被提供给多个感测放大器。

公开(公告)号：US20090093643A1

公开(公告)日：2009-04-09

申请号：US12084316

申请日：2006-10-30

申请人： Masao Morimoto ,  Atsushi Yamakawa

发明人： Masao Morimoto ,  Atsushi Yamakawa

IPC分类号： C07D207/16 ,  C07D207/12

CPC分类号： C07D207/12

摘要： Provided are: a process for production of a benzyloxypyrrolidine derivative in high yield and safety, and a process for production of a hydrochloride powder of a benzyloxypyrrolidine derivative in high yield and safety; the process for production of a benzyloxypyrrolidine derivative expressed by the general formula (2) [Chemical formula 2], in reacting a pyrrolidinol derivative represented by the general formula (1) [Chemical formula 1] with a benzyl halide derivative in the presence of an alkali metal hydroxide, wherein the reaction is carried out in either of the following conditions A or B; condition A: an aprotic polar solvent, and condition B: an aliphatic ether solvent containing a phase transfer catalyst:

摘要翻译： 本发明提供以高产率和安全的方式生产苄氧基吡咯烷衍生物的方法，以及高生产率和安全性生产苄氧基吡咯烷衍生物的盐酸盐粉末的方法; 在通式（2）[化学式2]表示的苄氧基吡咯烷衍生物的制备方法中，在通式（1）[化学式1]表示的吡咯烷醇衍生物与苄基卤衍生物在 碱金属氢氧化物，其中反应在以下任一条件A或B中进行; 条件A：非质子极性溶剂，条件B：含有相转移催化剂的脂族醚溶剂：

公开(公告)号：US20060161003A1

公开(公告)日：2006-07-20

申请号：US10524517

申请日：2003-09-02

申请人： Masao Morimoto ,  Haruyo Sato

发明人： Masao Morimoto ,  Haruyo Sato

IPC分类号： C07D241/04

CPC分类号： C07D295/205

摘要： If an organic solvent with a water content of 15% or less is used when an oxycarbonyl-substituted piperazine derivative is produced from a piperazine derivative, the piperazine derivative can be oxycarbonylated.

公开(公告)号：US4350472A

公开(公告)日：1982-09-21

申请号：US93596

申请日：1979-11-13

申请人： Masao Morimoto

发明人： Masao Morimoto

IPC分类号： F04D25/10 ,  F04D29/56

CPC分类号： F04D25/10

摘要： The present application discloses an electric fan apparatus comprising a fan, a wind direction shifting plate disposed in front of said fan and adapted to be rotated by the pressure of a wind generated by said fan, a rotary shaft disposed at the center of said wind direction shifting plate and adapted to be rotated integrally with said wind direction shifting plate, a speed governor mechanism interlocked with said rotary shaft and a housing box for housing said speed governor mechanism.With said wind direction shifting plate rotated, a wind may be provided in a wide range. Provision is made to improve the durability of said speed governor mechanism, which is formed with a gear mechanism and a blade. Said housing box contains a liquid into which at least a portion of said gear mechanism is immersed, so that said wind direction shifting plate is rotated at a substantially constant low speed.

摘要翻译： 本申请公开了一种电风扇装置，包括风扇，设置在所述风扇前面并适于由所述风扇产生的风的压力旋转的风向移动板，设置在所述风向中心的旋转轴 与所述风向移动板一体地旋转，与所述旋转轴联动的调速机构和用于容纳所述调速机构的收纳箱。 当所述风向移动板旋转时，可以在宽范围内提供风。 规定了用齿轮机构和叶片形成的所述调速机构的耐久性。 所述容纳箱包含浸入所述齿轮机构的至少一部分的液体，使得所述风向移动板以基本恒定的低速旋转。

公开(公告)号：USRE30933E

公开(公告)日：1982-05-18

申请号：US125750

申请日：1980-02-28

申请人： Kenzo Toda ,  Hisashi Gondo ,  Bunichiro Kawasaki ,  Mitsunobu Abe ,  Ryoseki Katsutani ,  Tsuyoshi Kawano ,  Norimasa Uehara ,  Yoshio Saito ,  Kenichiro Suemune ,  Masahiko Shiraishi ,  Yoshifumi Tadashige ,  Masao Morimoto ,  Takao Tsukamura ,  Kurayoshi Watanabe ,  Teruhiko Nishimura

发明人： Kenzo Toda ,  Hisashi Gondo ,  Bunichiro Kawasaki ,  Mitsunobu Abe ,  Ryoseki Katsutani ,  Tsuyoshi Kawano ,  Norimasa Uehara ,  Yoshio Saito ,  Kenichiro Suemune ,  Masahiko Shiraishi ,  Yoshifumi Tadashige ,  Masao Morimoto ,  Takao Tsukamura ,  Kurayoshi Watanabe ,  Teruhiko Nishimura

IPC分类号： B21B1/22 ,  B21B15/00 ,  B21B31/10 ,  B21B39/08 ,  C21D8/04 ,  C21D9/52 ,  C21D9/56 ,  C21D9/573

CPC分类号： C21D8/0426 ,  B21B31/10 ,  C21D8/0452 ,  C21D8/0473 ,  C21D9/52 ,  C21D9/56 ,  B21B2001/228 ,  B21B2015/0071 ,  B21B39/08 ,  C21D8/0436 ,  C21D8/0442 ,  C21D9/563 ,  C21D9/573

摘要： An apparatus for continuous treatment of cold rolled steel sheet. The apparatus has a continuous annealing furnace through which the sheet is continuously passed and which is composed of, in succession, a heating chamber for heating the cold rolled steel sheet to a temperature range of 700.degree. to 900.degree. C. within 2 minutes, a soaking chamber for keeping the sheet in the above temperature range for two minutes or less, a primary cooling chamber for rapidly cooling the sheet from the above temperature range to an overageing at a rate of 5.degree. to 30.degree. C./sec., an overageing chamber for keeping the sheet between 300.degree. to 400.degree. C. for up to eight minutes, and a secondary cooling chamber for cooling the sheet from the above overageing temperature to below 50.degree. C. within 2 minutes. Adjacent the output end of said furnace is apparatus for successively skin pass rolling, levelling and recoiling the sheet from the annealing furnace. The skin pass rolling apparatus has apparatus for replacing the working rolls.

公开(公告)号：US08854869B2

公开(公告)日：2014-10-07

申请号：US12855691

申请日：2010-08-12

申请人： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki ,  Yasuyuki Okuma ,  Toshiaki Sano

发明人： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki ,  Yasuyuki Okuma ,  Toshiaki Sano

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C5/06 ,  G11C11/413

CPC分类号： G11C11/417 ,  G11C5/06 ,  G11C5/14 ,  G11C11/413 ,  H01L27/092 ,  H01L27/1104

摘要： A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

摘要翻译： 提供了可以对备用时的保留数据量的变化进行响应的半导体集成电路。 半导体集成电路包括逻辑电路（逻辑）和多个SRAM模块。 多个SRAM模块独立于逻辑电路进行功率控制，并且在多个SRAM模块之间执行独立的功率控制。 具体地，每个SRAM模块的电位控制电路的一个端子和另一个端子分别耦合到单元阵列和本地电力线。 一个SRAM模块的本地电源线和另一个SRAM模块的本地电源线共享一个共享的本地电源线。 一个SRAM模块的电源开关和另一个SRAM模块的电源开关共同耦合到共享的本地电源线。

公开(公告)号：US20110063895A1

公开(公告)日：2011-03-17

申请号：US12855691

申请日：2010-08-12

申请人： Shigenobu KOMATSU ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki ,  Yasuyuki Okuma ,  Toshiaki Sano

发明人： Shigenobu KOMATSU ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki ,  Yasuyuki Okuma ,  Toshiaki Sano

IPC分类号： G11C11/417 ,  G11C11/412 ,  G11C5/14

CPC分类号： G11C11/417 ,  G11C5/06 ,  G11C5/14 ,  G11C11/413 ,  H01L27/092 ,  H01L27/1104

摘要： A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

摘要翻译： 提供了可以对备用时的保留数据量的变化进行响应的半导体集成电路。 半导体集成电路包括逻辑电路（逻辑）和多个SRAM模块。 多个SRAM模块独立于逻辑电路进行功率控制，并且在多个SRAM模块之间执行独立的功率控制。 具体地，每个SRAM模块的电位控制电路的一个端子和另一个端子分别耦合到单元阵列和本地电力线。 一个SRAM模块的本地电源线和另一个SRAM模块的本地电源线共享一个共享的本地电源线。 一个SRAM模块的电源开关和另一个SRAM模块的电源开关共同耦合到共享的本地电源线。