COMPUTING SYSTEM AND DATA TRANSPORT SYSTEM

    公开(公告)号:US20250141817A1

    公开(公告)日:2025-05-01

    申请号:US18383481

    申请日:2023-10-25

    Applicant: MEDIATEK INC.

    Inventor: Tsai-Chun Hsieh

    Abstract: A computing system comprising: routers, configured to transport data to nodes; transport stations, configured to transport the data to the nodes through the routers; first paths, provided between adjacent ones of the routers; second paths, provided between adjacent ones of the transport stations. The computing system operates in a first mode, which transmits the data from a first target device to a second target device via the first paths and the second paths.

    BUFFER CIRCUITS AND SEMICONDUCTOR STRUCTURES THEREOF

    公开(公告)号:US20250141446A1

    公开(公告)日:2025-05-01

    申请号:US19009332

    申请日:2025-01-03

    Applicant: MEDIATEK INC.

    Abstract: A buffer circuit is provided to output an output signal at an output node. The buffer circuit includes first and second inverters and first and second switches. The first inverter inverts an input signal. The second inverter is coupled between the first inverter and the output node. The first switch is coupled between a first voltage source terminal and the output node. The second switch is coupled between the output node and a second voltage source terminal. First and second voltages are respectively provided to the first and second voltage source terminals. In response to the input signal switching to a first level from a second level, the first switch is turned on to pre-charge the output node. In response to the input signal transiting to the second level from the first level, the second switch is turned on to pre-discharge the output node.

    Delay-aware bandwidth scheduling for wireless communication network

    公开(公告)号:US12289753B2

    公开(公告)日:2025-04-29

    申请号:US17533254

    申请日:2021-11-23

    Applicant: MEDIATEK INC.

    Abstract: A device is provided. The device includes: at least one antenna, a plurality of buffer sets, and a circuit. Each buffer set includes a plurality of queue buffers, and each queue buffer is dedicated for a respective application category. The circuit communicates with one or more stations through the at least one antenna. In response to the circuit determining that a plurality of incoming frames or packets are classified into the same application category, the circuit performs an intra-Access Category (intra-AC) scheduling mechanism to determine priorities of data stored in the queue buffers in the same application category according to QoS (quality-of-service) requirements of each station so as to arrange for an MU (multi-user) PPDU (physical-layer protocol data unit) to be transmitted to at least a portion of the stations.

    ACCESS POINT (AP) AND METHOD TO ACHIEVE SECURITY OF COORDINATED BEAMFORMING

    公开(公告)号:US20250133396A1

    公开(公告)日:2025-04-24

    申请号:US18917396

    申请日:2024-10-16

    Applicant: MEDIATEK INC.

    Abstract: A first access point (AP) in a multiple access points (MAP) system of a wireless network is provided. The MAP system further includes a second AP. The first AP includes a transceiver and a control circuit. The transceiver transmits and receives frames over the wireless network. The control circuit transmits a protected frame to a non-AP station associated to the second AP, and receives a response frame in response to the protected frame from the non-AP station.

    Method of Synchronization for Universal Serial Bus and System Thereof

    公开(公告)号:US20250130966A1

    公开(公告)日:2025-04-24

    申请号:US18381175

    申请日:2023-10-18

    Applicant: MEDIATEK INC.

    Abstract: A method of synchronization in a training state of Universal Serial Bus (USB) includes sending SLOS1 ordered sets by a transmitter in a LOCK1 state, receiving the SLOS1 ordered sets by a receiver in the LOCK1 state, stopping the transmitter from sending training ordered sets according to a lane adapter state machine (LASM) if the transmitter sends the training ordered sets in the LOCK1 state continuously in an infinite loop. The training ordered sets include the SLOS1 ordered sets. The method further includes sending new SLOS1 ordered sets by the transmitter, receiving the new SLOS1 ordered sets by a receiver, and the transmitter and the receiver entering a LOCK2 state. The length of the new SLOS1 ordered sets is different from the length of the SLOS1 ordered sets.

    PROCEDURES AND SIGNAL DESIGN FOR NTN NB-IOT WUR

    公开(公告)号:US20250126004A1

    公开(公告)日:2025-04-17

    申请号:US18903156

    申请日:2024-10-01

    Applicant: MEDIATEK INC.

    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE receiving a unified waveform signal from a base station, wherein the unified waveform signal comprises an On-Off Keying (OOK) signal and an Orthogonal Frequency Division Multiplexing (OFDM) signal; determining whether an indicator in the OFDM signal indicates that the unified waveform signal is a low-power wake-up signal (LP-WUS); decoding the LP-WUS when the indicator indicates that the unified waveform signal is the LP-WUS; and terminating a decoding operation when the indicator indicates that the unified waveform signal is not the LP-WUS.

    Method for adaptively adjusting state transition time in peripheral component interconnect express system to enhance overall performance, and associated apparatus

    公开(公告)号:US12277022B2

    公开(公告)日:2025-04-15

    申请号:US18096545

    申请日:2023-01-12

    Applicant: MEDIATEK INC.

    Inventor: Sheng-Ya Tung

    Abstract: A method for adaptively adjusting state transition time in a Peripheral Component Interconnect (PCI) Express (PCIe) system and associated apparatus such as a root complex (RC) device and an endpoint device are provided. The method may include: toggling a clock request signal on a signal path coupled between the RC device and the endpoint device based on a request from the RC device or on a request from the endpoint device, wherein when the clock request signal toggles, the endpoint device transits from a first state to a second state; and toggling a reference clock signal from the RC device at a timing determined according to a training parameter among at least one predetermined parameter which is set dependent on at least one of the factors: a transition time, a restoration delay, a latency tolerance report (LTR) and a bias state, after the clock request signal toggles.

    ELECTRONIC DEVICE AND METHOD OF HANDLING A SELF-ADAPTIVE MECHANISM

    公开(公告)号:US20250117229A1

    公开(公告)日:2025-04-10

    申请号:US18906139

    申请日:2024-10-03

    Applicant: MEDIATEK INC.

    Abstract: An electronic device includes a processor arranged to execute an application, a platform and a middleware. The application is configured to execute operations of: providing at least one acceptable quality and at least one priority of the at least one profile parameter. The platform is configured to execute an operation of: providing platform information in response to a demand request. The middleware is configured to execute operations of: receiving the at least one acceptable quality and the at least one priority from the application; receiving the platform information from the platform; performing a self-adaptive algorithm according to the platform information to generate a result; adjusting the at least one profile parameter according to the result, the at least one acceptable quality and the at least one priority; and transmitting an adjustment notification to the platform, after adjusting the at least one profile parameter.

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