公开(公告)号：US20060250291A1

公开(公告)日：2006-11-09

申请号：US11122587

申请日：2005-05-05

Applicant: Colin Lyden ,  Michael Coln ,  Robert Brewer

Inventor： Colin Lyden ,  Michael Coln ,  Robert Brewer

IPC: H03M1/12

CPC classification number: H03M1/08 ,  H03M1/122

Abstract: An accurate, low noise conditionally resetting integrator circuit in an analog to digital system samples, with an analog to digital converter, the output of an integrating circuit a number of times during a measuring period; isolates the input for the integrating circuit during sample event; generates a reset signal in response to the integrating circuit output reaching a predetermined level; and resets the feedback capacitor of the integrating circuit by isolating it from the amplifier circuit of the integrating circuit and connecting it to a reference source during a sample event.

Abstract translation: 模拟数字系统中的精确低噪声有条件复位积分电路采样模数转换器，在测量期间多次输出积分电路; 在采样事件期间隔离积分电路的输入; 响应于所述积分电路输出达到预定水平而产生复位信号; 并且通过将其与积分电路的放大器电路隔离并且在采样事件期间将其连接到参考源来复位积分电路的反馈电容器。

公开(公告)号：US20060176197A1

公开(公告)日：2006-08-10

申请号：US11349400

申请日：2006-02-06

Applicant: John McNeill ,  Michael Coln

Inventor： John McNeill ,  Michael Coln

IPC: H03M1/10

CPC classification number: H03M1/1004 ,  H03M1/0643

Abstract: A calibratable analog-to-digital converter system with a split analog-to-digital converter architecture including N Analog-to-Digital Converters (ADCs) each configured to convert the same analog input signal into a digital signal. Calibration logic is responsive to the digital signals output by the N ADCs and is configured to calibrate each of the ADCs based on the digital signals output by each ADC.

Abstract translation: 具有分立模数转换器架构的可校准模数转换器系统，包括N个模拟数字转换器（ADC），每个模拟数字转换器配置为将相同的模拟输入信号转换为数字信号。 校准逻辑响应由N个ADC输出的数字信号，并且被配置为基于每个ADC输出的数字信号校准每个ADC。

公开(公告)号：US5804957A

公开(公告)日：1998-09-08

申请号：US910285

申请日：1997-08-13

Applicant: Michael Coln

Inventor： Michael Coln

IPC: A61N1/30 ,  A61N1/32 ,  G05F1/575 ,  H02M3/156 ,  G05F1/56 ,  A61N1/18

CPC classification number: A61N1/0432 ,  A61N1/30 ,  A61N1/325 ,  G05F1/575 ,  H02M3/156

Abstract: A constant current supply system for a variable resistance load includes first and second output terminals for applying a predetermined current to a variable resistance load; a constant current circuit connected to the second output terminal for providing the predetermined current to the load; a voltage supply connected to the first terminal for providing a voltage across the terminal and constant current circuit; and a voltage supply control circuit for monitoring the voltage at the second terminal across the constant current circuit and adjusting the voltage supply to maintain the second terminal at a preselected voltage for maintaining the predetermined current to the variable resistance load.

Abstract translation: 用于可变电阻负载的恒定电流供应系统包括用于向可变电阻负载施加预定电流的第一和第二输出端子; 连接到第二输出端子的恒流电路，用于向负载提供预定电流; 连接到第一端子的电压源，用于在端子和恒流电路两端提供电压; 以及电压供给控制电路，用于监视跨过恒流电路的第二端子处的电压，并调整电压供应，以将第二端子保持在预选电压，以将预定电流保持在可变电阻负载上。

公开(公告)号：US5475628A

公开(公告)日：1995-12-12

申请号：US954149

申请日：1992-09-30

Applicant: Robert W. Adams ,  Tom W. Kwan ,  Michael Coln

Inventor： Robert W. Adams ,  Tom W. Kwan ,  Michael Coln

IPC: H03H17/00 ,  H03H17/02 ,  H03H17/06 ,  G06F17/17

CPC classification number: H03H17/0628

Abstract: An asynchronous digital sample rate converter includes a random access memory for storing input data values and a read only memory for storing a reduced set of interpolation filter coefficients. Input data is written to the random access memory at the input sample rate. Output samples are provided from a multiply/accumulate engine which given a stream of input data and filter coefficients produces an output sample upon request at the output frequency. The initial address for reading input data from the random access memory, and the addresses for coefficients from the read only memory are provided by an auto-centering scheme which is a first order closed loop system with a digital integrator fed by an approximation of the input to output sample rate ratio. This auto-centering scheme may include a feed forward low pass filter to cancel steady state error, and an interpolated write address to reduce noise. A circuit determining the output to input sample rate ratios can also be provided to scale coefficient addresses and resulting output samples to allow for decimation. This circuit includes a form of digital hysteresis to eliminate noise. The ROM coefficients are reduced by relying on the symmetry of the impulse response of the interpolation filter and by utilizing a variable step size forward and backward linear interpolation.

公开(公告)号：US20130329853A1

公开(公告)日：2013-12-12

申请号：US13493775

申请日：2012-06-11

Applicant: Michael COLN ,  Paraic BRANNICK ,  Colin G. LYDEN ,  Cathal MURPHY

Inventor： Michael COLN ,  Paraic BRANNICK ,  Colin G. LYDEN ,  Cathal MURPHY

IPC: H05G1/60 ,  G06G7/18

CPC classification number: G06G7/186

Abstract: A detector circuit can include an integrator having an amplifier, a first feedback capacitor connected between an input and output of the amplifier, one or more additional feedback capacitors connected by at least one switch between the input and output of the amplifier, and a shunt capacitor connected to the output of the amplifier. The shunt capacitor can be selected to have a capacitance value greater than that of a minimum but less than that of a maximum feedback capacitance. The detector circuit can further include a sampling circuit having a sampling capacitor connected to the output of the integrator amplifier through at least one switch, wherein the sampling capacitor is separate from the shunt capacitor. A computed tomography imaging apparatus can include the detector circuit.

Abstract translation: 检测器电路可以包括具有放大器的积分器，连接在放大器的输入和输出之间的第一反馈电容器，通过放大器的输入和输出之间的至少一个开关连接的一个或多个附加反馈电容器和分流电容器 连接到放大器的输出。 可以选择并联电容器的电容值大于最小但小于最大反馈电容的电容值。 检测器电路还可以包括采样电路，该采样电路具有通过至少一个开关连接到积分放大器的输出的采样电容器，其中采样电容器与分流电容器分离。 计算机断层成像设备可以包括检测器电路。

公开(公告)号：US08525299B2

公开(公告)日：2013-09-03

申请号：US13786646

申请日：2013-03-06

Applicant: Lejun Hu ,  Srivatsan Parthasarathy ,  Michael Coln ,  Javier Salcedo

Inventor： Lejun Hu ,  Srivatsan Parthasarathy ,  Michael Coln ,  Javier Salcedo

IPC: H01L27/02

CPC classification number: H01L29/0646 ,  H01L23/481 ,  H01L27/0255 ,  H01L27/1446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications.

Abstract translation: 形成在衬底上的半导体器件包括第一二极管结形成，第二二极管结形成以及至少一个通硅通孔（TSV），其中第一二极管的阴极和阳极交叉连接到 通过至少一个TSV来实现第二二极管的阳极和阴极，以实现基于硅通孔的集成电路中的电鲁棒性，包括用于信号处理应用的光敏器件和电路。

公开(公告)号：US20130175669A1

公开(公告)日：2013-07-11

申请号：US13786646

申请日：2013-03-06

Applicant: Lejun HU ,  Srivatsan Parthasarathy ,  Michael COLN ,  Javier SALCEDO

Inventor： Lejun HU ,  Srivatsan Parthasarathy ,  Michael COLN ,  Javier SALCEDO

IPC: H01L29/06

CPC classification number: H01L29/0646 ,  H01L23/481 ,  H01L27/0255 ,  H01L27/1446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device formed on a substrate includes a first diode junction formation, a second diode junction formation, and at least one through-silicon-via (TSV), in which a cathode and an anode of the first diode are cross-connected to an anode and cathode of the second diode through the at least one TSV for achieving electrical robustness in through-silicon-via based integrated circuits, including photosensitive devices and circuits for signal processing applications.

公开(公告)号：US20120200350A1

公开(公告)日：2012-08-09

申请号：US13023751

申请日：2011-02-09

Applicant: Cathal MURPHY ,  Michael COLN ,  Gary CARREAU ,  Alain Valentin GUERY ,  Bruce AMAZEEN

Inventor： Cathal MURPHY ,  Michael COLN ,  Gary CARREAU ,  Alain Valentin GUERY ,  Bruce AMAZEEN

IPC: H03F1/34 ,  H02M3/06

CPC classification number: H03F1/34 ,  H03F3/45475 ,  H03F3/68 ,  H03F2203/45514

Abstract: An amplifier system can include a feedback amplifier circuit having an amplifier, a feedback capacitor connected between an input terminal and an output terminal of the amplifier by at least one first switch, and a reset capacitor connected across the feedback capacitor by at least one second switch and between a pair of reference voltages by at least one third switch. During an input-signal processing phase of operation, a control circuit may close the at least one first switch and open the at least one second switch to electrically connect the feedback capacitor between the input and output terminals to engage feedback processing by the feedback amplifier circuit, and close the third switch to electrically connect the reset capacitor between the first and second voltages to charge the reset capacitor to a selectable voltage difference. During a reset phase of operation, the control circuit may open the at least one third switch, close the at least one second switch and open the at least one first switch to electrically connect the reset capacitor across the feedback capacitor to reset the feedback capacitor using the reset capacitor. The amplifier system can optionally include a plurality of the feedback amplifier circuits.

Abstract translation: 放大器系统可以包括具有放大器的反馈放大器电路，通过至少一个第一开关连接在放大器的输入端子和输出端子之间的反馈电容器以及通过至少一个第二开关连接在反馈电容器上的复位电容器 以及通过至少一个第三开关在一对参考电压之间。 在操作的输入信号处理阶段期间，控制电路可以关闭所述至少一个第一开关并且打开所述至少一个第二开关以将所述反馈电容器电连接在所述输入和输出端子之间，以接收所述反馈放大器电路的反馈处理 并且关闭第三开关以在第一和第二电压之间电连接复位电容器，以将复位电容器充电至可选择的电压差。 在操作的复位阶段期间，控制电路可以打开至少一个第三开关，闭合至少一个第二开关并且打开至少一个第一开关，以使反馈电容器上的复位电容器电连接以使反馈电容器复位以使用 复位电容。 放大器系统可以可选地包括多个反馈放大器电路。

公开(公告)号：US08228217B2

公开(公告)日：2012-07-24

申请号：US12846649

申请日：2010-07-29

Applicant: Lalinda Fernando ,  Michael Coln

Inventor： Lalinda Fernando ,  Michael Coln

IPC: H03M1/48

CPC classification number: H03M1/0626 ,  H03M1/645

Abstract: A system and method for reducing noise in resolver-to-digital converters (RDC) using a cascaded tracking loop filter. In some embodiments, one or more tracking loop filters may be implemented in a cascade to attenuate carrier harmonic frequencies in the digitized output of an RDC. Where a plurality of tracking loop filters are implemented, the output of one tracking loop filter may be input into a successive tracking loop filter.

Abstract translation: 一种使用级联跟踪环路滤波器降低分解数字转换器（RDC）中噪声的系统和方法。 在一些实施例中，可以级联地实现一个或多个跟踪环路滤波器，以衰减RDC的数字化输出中的载波谐波频率。 在实现多个跟踪环路滤波器的情况下，一个跟踪环路滤波器的输出可被输入到连续的跟踪环路滤波器中。

公开(公告)号：US08203357B2

公开(公告)日：2012-06-19

申请号：US12630999

申请日：2009-12-04

Applicant: Yoshinori Kusuda ,  Michael Coln ,  Gary Carreau

Inventor： Yoshinori Kusuda ,  Michael Coln ,  Gary Carreau

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03M1/0818 ,  H03M1/1225

Abstract: An integrated circuit may include a plurality of circuit sub-systems that include at least one converter circuit operating in respective critical phases and non-critical phases of operation, a clock distribution circuit that has an input for an externally-supplied clock signal that is active during the non-critical phases and inactive during the critical phases, and a clock generator to generate an internal clock signal to the converter circuit that is active when the external-supplied clock signal is inactive.

Abstract translation: 集成电路可以包括多个电路子系统，其包括在相应的临界相位和非临界相位操作中操作的至少一个转换器电路，具有用于外部提供的时钟信号的输入的时钟分配电路是有效的 在非临界阶段期间在关键阶段期间不起作用，以及时钟发生器，用于在外部提供的时钟信号无效时，向转换器电路产生内部时钟信号，该转换器电路有效。