公开(公告)号：US20120133407A1

公开(公告)日：2012-05-31

申请号：US13292133

申请日：2011-11-09

申请人： Masanao YOKOYAMA ,  Noboru OKUZONO

发明人： Masanao YOKOYAMA ,  Noboru OKUZONO

IPC分类号： H03K3/037

CPC分类号： G09G3/3611 ,  G09G2310/0264 ,  G09G2310/08 ,  H03K3/012 ,  H03K3/356156 ,  H03K3/35625

摘要： An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks.

摘要翻译： 输入缓冲器根据第一控制时钟选择输出输入数据信号或输出高阻抗信号。 主触发器根据第二控制时钟选择输出从输入缓冲器接收的数据信号或保持当前输出的数据信号。 主从开关根据第二控制时钟选择输出高阻抗信号或输出从主触发器接收的数据信号。 从触发器根据第二控制时钟选择保持当前输出的数据信号或输出从主从交换机接收的数据信号。 时钟缓冲器输入第二控制时钟，并产生并输出第一控制时钟。

公开(公告)号：US07126572B2

公开(公告)日：2006-10-24

申请号：US10396329

申请日：2003-03-26

申请人： Koichi Koga ,  Noboru Okuzono ,  Machihiko Yamaguchi

发明人： Koichi Koga ,  Noboru Okuzono ,  Machihiko Yamaguchi

IPC分类号： G09G3/36 ,  G09G5/10

CPC分类号： G09G3/2025 ,  G09G3/2003 ,  G09G3/2077 ,  G09G3/2092 ,  G09G3/3648 ,  G09G5/02 ,  G09G2320/0233 ,  G09G2320/0247

摘要： A display panel 13 having a plurality of pixels 14 each divided into P (P=3) sub-pixels 15a, 15b and 15c, and a source driver 12 for driving each pixel 14 in accordance with three J (=8)-bit data values corresponding to the sub-pixels 15a, 15b, and 15c, and a signal processing circuit 12 for distributing K(=12)-bit (K>J) input image data as M (M=6) time-shared frame data values and supplying the frame data values to the source driver 12 are arranged. 2K−J (=16) gray levels insufficient due to the difference between the numbers of bits of K-bit input image data and J-bit driving signals of the source driver 12 is realized by combinations of time-shared frame data of (P×M=18) ways performed for the sub-pixels 15a, 15b, and 15c in accordance with the M time-shared frame data values.

摘要翻译： 具有分成P（P = 3）个子像素15a，15b和15c的多个像素14的显示面板13以及根据三个J（= 8）驱动每个像素14的源极驱动器12， 对应于子像素15 a，15 b和15 c的位数据值，以及用于将K（= 12）位（K> J）输入图像数据分配为M（M = 6）的信号处理电路12， 布置了时间共享帧数据值并将帧数据值提供给源驱动器12。 由于K位输入图像数据的位数和源极驱动器12的J位驱动信号之间的差异，由于时间 - 频率的组合实现了2kHz（= 16）的灰度级， 根据M个时间共享帧数据值对子像素15 a，15 b和15 c执行的（PxM = 18）方式的共享帧数据。

公开(公告)号：US06982693B2

公开(公告)日：2006-01-03

申请号：US10762502

申请日：2004-01-23

申请人： Noboru Okuzono ,  Koichi Koga

发明人： Noboru Okuzono ,  Koichi Koga

IPC分类号： G09G3/36

CPC分类号： G09G3/3614 ,  G09G3/3648 ,  G09G2320/0204 ,  G09G2320/0223

摘要： A liquid crystal display is provided which has low power consumption, and which prevents horizontal stripes from occurring without the circuitry becoming more complex. When the write voltage polarity is inverted every plurality of lines, in the n line where the polarity is inverted, the rise in the drain line waveform dulls due to the charging of the drain line. In the n+1 line, because the drain line has been charged by the writing of the n line, waveform dullness does not occur. A difference between the write states in the two lines causes horizontal stripes. Consequently, the output enable signal is activated at the rise of the clock signal, and the gate line is activated after a predetermined time to start the writing. Therefore, writing is not performed during the period of waveform dullness, and the write state is the same across all scan lines.

摘要翻译： 提供了具有低功耗的液晶显示器，并且防止水平条纹发生，而电路变得更加复杂。 当写入电压极性每多行反转时，在极性反转的n行中，由于漏极线的充电，漏极线波形的上升变钝。 在n + 1行中，由于通过n行的写入对漏极线进行了充电，因此不会发生波形钝化。 两行之间写入状态之间的差异会导致水平条纹。 因此，在时钟信号的上升时，输出使能信号被激活，并且在开始写入的预定时间之后激活栅极线。 因此，在波形迟钝期间不进行写入，写入状态在所有扫描线上相同。

公开(公告)号：US06894673B2

公开(公告)日：2005-05-17

申请号：US10192101

申请日：2002-07-10

申请人： Koichi Koga ,  Noboru Okuzono ,  Machihiko Yamaguchi

发明人： Koichi Koga ,  Noboru Okuzono ,  Machihiko Yamaguchi

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  H04N5/66

CPC分类号： G09G3/3611 ,  G09G3/3677

摘要： A liquid crystal display control circuit receives a data enable signal DE in synchronization with per-line based display data from a computer, and thereby controls a liquid crystal display. A gate drive signal outputted from a gate driver 23 is generated according to a vertical clock signal VCK in synchronization with a rise of the signal DE. In order to avoid a variation in the period of charging the pixel electrodes which is caused by a delay in the rise timing of the signal DE and a delay in the signal VCK after the last line, a gate enable signal generation circuit 10 is provided in the liquid crystal display control circuit 1, whereby the extended output of the pulse of the gate drive signal caused by the above-mentioned delays is inhibited. This avoids display inhomogeneity caused by a variation in the data enable signal and the like.

摘要翻译： 液晶显示控制电路与来自计算机的基于行的显示数据同步地接收数据使能信号DE，从而控制液晶显示器。 与信号DE的上升同步地，根据垂直时钟信号VCK产生从栅极驱动器23输出的栅极驱动信号。 为了避免由于信号DE的上升时间的延迟和最后一行之后的信号VCK中的延迟引起的像素电极的充电周期的变化，栅极使能信号生成电路10被设置在 液晶显示控制电路1，由此抑制由上述延迟引起的栅极驱动信号的脉冲的扩展输出。 这避免了由数据使能信号等的变化引起的显示不均匀性。

公开(公告)号：US06473066B1

公开(公告)日：2002-10-29

申请号：US09550875

申请日：2000-04-17

申请人： Noboru Okuzono

发明人： Noboru Okuzono

IPC分类号： G09G336

CPC分类号： G09G3/3648 ,  G09G3/20 ,  G09G2310/0224 ,  G09G2310/0297

摘要： A method of driving a display apparatus, includes (a) providing a plurality of processors outputting a plurality of output signals, respectively; (b) providing a plurality of frames, wherein each of the plurality of frames has an averaging pattern for averaging characteristic errors of the plurality of processors and has a plurality of lines; (c) performing a first scanning on a predetermined frame of the plurality of frames such that a predetermined line of the plurality of lines of the predetermined frame is not scanned; and (d) performing a second scanning on a specific frame of the plurality of frames such that a line corresponding to the predetermined line of the specific frame is scanned, the specific frame having a same averaging pattern as the averaging pattern of the predetermined frame.

摘要翻译： 一种驱动显示装置的方法，包括：（a）提供分别输出多个输出信号的多个处理器; （b）提供多个帧，其中所述多个帧中的每一个具有用于对所述多个处理器的特征误差进行平均的平均模式，并且具有多条线; （c）对所述多个帧的预定帧执行第一扫描，使得所述预定帧的所述多条行的预定行不被扫描; 以及（d）对所述多个帧的特定帧执行第二扫描，使得对应于所述特定帧的预定行的行被扫描，所述特定帧具有与所述预定帧的平均模式相同的平均模式。

公开(公告)号：US20090195272A1

公开(公告)日：2009-08-06

申请号：US12320644

申请日：2009-01-30

申请人： Noboru Okuzono

发明人： Noboru Okuzono

IPC分类号： H03L7/00

CPC分类号： H03K5/15026 ,  G09G3/20 ,  G09G2310/027 ,  G09G2310/08 ,  G09G2370/08 ,  H03K5/133 ,  H03K2005/00032 ,  H03L7/0812 ,  H03L7/0995 ,  H03M9/00

摘要： A receiver circuit is provided with: a plurality of input terminals; a plurality of hold circuits holding reception signals received by the plurality of input terminals; a detector circuit detecting clock bits from selected one of the reception signals to recover a clock signal in response to the detected clock bits; and a clock circuit connected to the detector circuit and generating one or more internal clock signals from the clock signal. The hold circuits commonly receive the internal clock signal(s) and perform sampling of the reception signals commonly in synchronization with the internal clock signal(s).

摘要翻译： 接收器电路设置有：多个输入端子; 多个保持电路，保持由所述多个输入端子接收的接收信号; 检测器电路，用于检测所选接收信号中的时钟位，以便响应所检测的时钟位来恢复时钟信号; 以及连接到检测器电路并从时钟信号产生一个或多个内部时钟信号的时钟电路。 保持电路通常接收内部时钟信号，并且通常与内部时钟信号同步地执行接收信号的采样。

公开(公告)号：US20090109077A1

公开(公告)日：2009-04-30

申请号：US12289266

申请日：2008-10-23

申请人： Hiroshi Tsuchi ,  Noboru Okuzono

发明人： Hiroshi Tsuchi ,  Noboru Okuzono

IPC分类号： H03M1/66

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  H03M1/661 ,  H03M1/68 ,  H03M1/76

摘要： Disclosed is a digital-to-analog converter circuit having first to (2×h+1)th reference voltages (where h is a prescribed positive integer) grouped into the following groups: a first reference voltage group comprising h-number of (2×j−1)th (where j is a prescribed positive integer of 1 to h) reference voltages; a second reference voltage group comprising h-number of (2×j)th reference voltages; and a third reference voltage group comprising h-number of (2×j+1)th reference voltages. The digital-to-analog converter circuit includes: a first subdecoder for receiving the first reference voltage group and selecting a reference voltage Vrk based upon an input digital signal; a second subdecoder for receiving the second reference voltage group and selecting a reference voltage Vr(k+1) based upon the input digital signal; a third subdecoder for receiving the third reference voltage group and selecting a reference voltage Vr(k+2) based upon the input digital signal; a fourth subdecoder for receiving the reference voltages Vr, Vr(k+1), and Vr(k+2) that have been selected by respective one of the first to third subdecoders, selecting two of these reference voltages (inclusive of selecting the same voltage redundantly) based upon an input digital signal, and outputting the selected two reference voltages; and an amplifier circuit for receiving the two reference voltages that have been selected by the fourth subdecoder and outputting result of an operation applied to the two reference voltages.

摘要翻译： 公开了一种数模转换器电路，其具有分组为以下组的第一至第（2xh + 1）参考电压（其中h是规定的正整数）：第一参考电压组，包括h个数量的（2xj-1 ）th（其中j是1至h的规定正整数）参考电压; 第二参考电压组，包括h个第（2xj）个参考电压; 以及包括h个（第（x + 1）个）参考电压的第三参考电压组。 数模转换器电路包括：第一子编码器，用于接收第一参考电压组并基于输入的数字信号选择参考电压Vrk; 第二子编码器，用于接收第二参考电压组，并且基于输入的数字信号选择参考电压Vr（k + 1）; 第三子编码器，用于接收第三参考电压组并基于输入的数字信号选择参考电压Vr（k + 2）; 用于接收由第一至第三子编码器中的相应一个选择的参考电压Vr，Vr（k + 1）和Vr（k + 2）的第四子编码器，选择这些参考电压中的两个（包括选择相同的） 电压冗余），并输出所选择的两个参考电压; 以及放大器电路，用于接收由第四子编码器选择的两个参考电压并输出施加到两个参考电压的操作结果。

公开(公告)号：US07030852B2

公开(公告)日：2006-04-18

申请号：US10122240

申请日：2002-04-16

申请人： Masahiro Ito ,  Kazuhiko Takami ,  Noboru Okuzono

发明人： Masahiro Ito ,  Kazuhiko Takami ,  Noboru Okuzono

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3666 ,  G09G5/005 ,  G09G5/006 ,  G09G2352/00

摘要： A liquid crystal display (LCD) panel unit is provided with a plurality of source drivers which are functionally divided into first and second source driver groups respectively assigned to first and second halves of an LCD panel. In order to properly drive the LCD panel irrespective of incoming pixel data of different formats, a pixel data rearrangement circuit is provided for rearranging the incoming pixel data to a predetermined data format. The data rearrangement circuit precedes the first and second source driver groups, and functions such as to receive 2N-path (N is a natural number) pixel data and rearranges the orders of the 2N-path pixel data according to the predetermined data format, and applies the rearranged N-path pixel data to the first source driver group and applying the rearranged other N-path pixel data to the second source driver group.

公开(公告)号：US06727874B2

公开(公告)日：2004-04-27

申请号：US09988189

申请日：2001-11-19

申请人： Noboru Okuzono

发明人： Noboru Okuzono

IPC分类号： G09G336

CPC分类号： G09G3/2011 ,  G09G3/3611 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2320/0276

摘要： A driving circuit of a color liquid crystal display is provided which is capable of reducing a substrate packaging area and using a common substrate or TCP (Tape Carrier Package) even when a resolution and/or the number of gray scale voltages that the color liquid crystal display provides are different, which enables the substrate, TCP, and a display device to be fabricated at low costs. In the driving circuit of the color liquid crystal display, a data electrode driving circuit produces gray scale voltages corresponding to gray scale voltage characteristics based on serial data made up of gray scale information and gray scale voltage information.

摘要翻译： 提供了一种彩色液晶显示器的驱动电路，即使在彩色液晶显示器的分辨率和/或灰度级电压数量分辨率和/或数量时，也能够减小基板封装区域并使用公共基板或TCP（带载封装） 显示提供是不同的，这使得能够以低成本制造基板，TCP和显示装置。 在彩色液晶显示器的驱动电路中，数据电极驱动电路基于由灰度信息和灰度级电压信息构成的串行数据，产生与灰度级电压特性相对应的灰度电压。