公开(公告)号：US06732259B1

公开(公告)日：2004-05-04

申请号：US09364789

申请日：1999-07-30

申请人： Radhika Thekkath ,  G. Michael Uhler ,  Ying-wai Ho ,  Chandlee B. Harrell

发明人： Radhika Thekkath ,  G. Michael Uhler ,  Ying-wai Ho ,  Chandlee B. Harrell

IPC分类号： G06F930

CPC分类号： G06F9/30014 ,  G06F9/30094 ,  G06F9/3885

摘要： A processor having a conditional branch extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision data formats, as well as the paired-single data format that allows two simultaneous operations on a pair of operands. The extension includes instructions directed to branching if, for example, either one of two condition codes is false or true, if any of three condition codes are false or true, or if any one of four condition codes are false or true.

摘要翻译： 具有包含一组高性能浮点运算的指令集架构的条件分支扩展的处理器。 指令集架构包含多种数据格式，包括单精度和双精度数据格式，以及允许在一对操作数上同时进行两次操作的配对单数据格式。 如果两个条件代码中的任一个为假或真，如果三个条件代码中的任何一个为假或真，或者四个条件代码中的任何一个为假或真，则扩展包括指向分支的指令。

公开(公告)号：US06681283B1

公开(公告)日：2004-01-20

申请号：US09373094

申请日：1999-08-12

申请人： Radhika Thekkath ,  G. Michael Uhler

发明人： Radhika Thekkath ,  G. Michael Uhler

IPC分类号： G06F1300

CPC分类号： G06F12/0815

摘要： A cache coherency system for an on-chip computing bus is provided. The coherency system contains a coherency credit counter within each master device on the on-chip bus for monitoring the resources available on the bus for coherent transactions, a coherency input buffer for storing coherent transactions, and a cache for storing coherent data. The coherency credit counter tracks coherent transactions pending in a memory controller, and delays coherent transactions from being placed on the bus if coherent resources are not available in the memory controller. When resources become available in the memory controller, the memory controller signals the coherency system in each of the master devices. The coherency system is coupled to a split transaction tracking and control to establish transaction ID's for each coherent transaction initiated by its master device, and presents a transaction ID along with an address portion of each coherent transaction.

摘要翻译： 提供了用于片上计算总线的高速缓存一致性系统。 一致性系统在片上总线上的每个主设备中包含一个相干性信用计数器，用于监视总线上可用于相干事务的资源，用于存储相干事务的一致性输入缓冲器以及用于存储相干数据的高速缓存。 相干信用计数器跟踪存储器控制器中等待的相干事务，并且如果在存储器控制器中不可用相干资源，则将相干事务延迟放置在总线上。 当存储器控制器中的资源变得可用时，存储器控制器向每个主设备中的相关系统发信号。 相关系统耦合到分割事务跟踪和控制，以为由其主设备发起的每个相干事务建立事务ID，并且将交易ID与每个相干事务的地址部分一起呈现。

公开(公告)号：US06434649B1

公开(公告)日：2002-08-13

申请号：US09173297

申请日：1998-10-14

申请人： David Baker ,  Christopher Basoglu ,  Benjamin Cutler ,  Gregorio Gervasio ,  Woobin Lee ,  Yatin Mundkur ,  Toru Nojiri ,  John O'Donnell ,  David Poole ,  Ashok Raman ,  Eric Rehm ,  Radhika Thekkath

发明人： David Baker ,  Christopher Basoglu ,  Benjamin Cutler ,  Gregorio Gervasio ,  Woobin Lee ,  Yatin Mundkur ,  Toru Nojiri ,  John O'Donnell ,  David Poole ,  Ashok Raman ,  Eric Rehm ,  Radhika Thekkath

IPC分类号： G06F1300

CPC分类号： G06F13/30 ,  G06F13/1605

摘要： In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.

摘要翻译： 在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线 其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。 处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。 处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。内部存储器总线被配置为从预定数量接收地址和数据信息 的模块，包括内存和I / O设备。 内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。 收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

公开(公告)号：US08230202B2

公开(公告)日：2012-07-24

申请号：US12060204

申请日：2008-03-31

申请人： Thomas Benjamin Berg ,  Ryan C. Kinter ,  Jaidev Prasad Patwardhan ,  Radhika Thekkath

发明人： Thomas Benjamin Berg ,  Ryan C. Kinter ,  Jaidev Prasad Patwardhan ,  Radhika Thekkath

IPC分类号： G06F9/30

CPC分类号： G06F11/3636 ,  G06F12/0815

摘要： A computer readable storage medium includes executable instructions to characterize a coherency controller. The executable instructions define ports to receive processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a condensed coherence indicator. Circuitry produces a trace stream with trace metrics and condensed coherence indicators.

摘要翻译： 计算机可读存储介质包括用于表征一致性控制器的可执行指令。 可执行指令定义从一组处理器接收处理器跟踪信息的端口。 来自每个处理器的处理器跟踪信息包括处理器标识和缩合相干指示符。 电路产生具有跟踪量度和浓缩相干指标的跟踪流。

公开(公告)号：US08024539B2

公开(公告)日：2011-09-20

申请号：US12021110

申请日：2008-01-28

申请人： Radhika Thekkath

发明人： Radhika Thekkath

IPC分类号： G06F12/00

CPC分类号： G06F12/1483

摘要： A processor-based method, system and apparatus to comprise a method, system and apparatus to access a memory location in an on-chip memory based on a virtual processing element identification associated with an instruction. The system comprises multiple virtual processing elements, an access list and a comparator coupled to the memory and the access list. In response to an instruction from a virtual processing element to access a memory location in the memory, the comparator compares a first virtual processing identification associated with the instruction to a second virtual processing identification stored in the access list and grants access to the virtual processing element that generated the instruction to read from or write to the memory location if the first virtual processing element identification is equal to the second virtual processing element identification. The data in the memory is allocated and de-allocated by software.

摘要翻译： 一种基于处理器的方法，系统和装置，其包括基于与指令相关联的虚拟处理单元识别来访问片上存储器中的存储器位置的方法，系统和装置。 该系统包括多个虚拟处理元件，访问列表和耦合到存储器和访问列表的比较器。 响应于来自虚拟处理元件的访问存储器中的存储器位置的指令，比较器将与指令相关联的第一虚拟处理标识与存储在访问列表中的第二虚拟处理标识进行比较，并授予对虚拟处理元件的访问 如果第一虚拟处理元件标识等于第二虚拟处理元件标识，则产生从存储器位置读取或写入存储器位置的指令。 存储器中的数据由软件分配和分配。

公开(公告)号：US07886129B2

公开(公告)日：2011-02-08

申请号：US10923584

申请日：2004-08-20

申请人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

发明人： Lawrence Henry Hudepohl ,  Darren Miller Jones ,  Radhika Thekkath ,  Franz Treue

IPC分类号： G06F9/312

CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859

摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.

摘要翻译： 提供了中央处理单元（CPU）和协处理器之间的可配置协处理器接口。 协处理器接口具有用于将不同指令类型从CPU向协处理器顺序或并行传送到忙信号组的指令传送信号组，用于允许协处理器向CPU发信号通知其不能接收一个或多个 不同的指令类型和用于向协处理器指示并行传送的多个指令的相对执行顺序的指令顺序信号组。 此外，协处理器接口包括用于从CPU传输到协处理器的数据的分离的数据传输信号组，以及用于指示数据的相对顺序的数据顺序信号组（从协处理器传送到CPU） 如果无序转移）。 该接口还包括允许CPU和一个或多个协处理器之间的多个问题组的信号指定。

公开(公告)号：US07721075B2

公开(公告)日：2010-05-18

申请号：US11336938

申请日：2006-01-23

申请人： Radhika Thekkath ,  Karagada Ramarao Kishore ,  Vidya Rajagopalan ,  Kevin D. Kissell

发明人： Radhika Thekkath ,  Karagada Ramarao Kishore ,  Vidya Rajagopalan ,  Kevin D. Kissell

IPC分类号： G06F9/40

CPC分类号： G06F9/3004 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/383 ,  G06F9/384

摘要： A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data mover engine such that, for the duration of the associations, the data mover engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.

摘要翻译： 具有数据移动器引擎的RISC处理器和将寄存器地址与存储器地址相关联的指令。 在一个实施例中，指令包括读取连接指令，单个写入指令，双重写入指令和解开指令。 读带，单写和双写指令用于将软件可访问寄存器地址与存储器地址相关联。 这些关联影响数据移动器引擎的操作，使得在关联的持续时间内，数据移动器引擎响应于指定移动数据到和从...移动数据的指令，将数据路由到相关联的存储器地址和处理器的执行单元 关联的寄存器地址。 本发明减少了与RISC处理器中实现程序循环相关联的指令数量和硬件开销。

公开(公告)号：US07721073B2

公开(公告)日：2010-05-18

申请号：US11336923

申请日：2006-01-23

申请人： Radhika Thekkath ,  Georgi Zlatkov Beloev

发明人： Radhika Thekkath ,  Georgi Zlatkov Beloev

IPC分类号： G06F9/40

CPC分类号： G06F9/3004 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/35 ,  G06F9/384

摘要： A RISC processor having a data moving engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data moving engine such that, for the duration of the associations, the data moving engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.

摘要翻译： 具有数据移动引擎的RISC处理器和将寄存器地址与存储器地址相关联的指令。 在一个实施例中，指令包括读取连接指令，单个写入指令，双重写入指令和解开指令。 读带，单写和双写指令用于将软件可访问寄存器地址与存储器地址相关联。 这些关联影响数据移动引擎的操作，使得在关联期间，数据移动引擎响应于指定移动数据到和从...移动数据的指令，将数据路由到相关联的存储器地址和处理器的执行单元 关联的寄存器地址。 本发明减少了与RISC处理器中实现程序循环相关联的指令数量和硬件开销。

公开(公告)号：US20070192567A1

公开(公告)日：2007-08-16

申请号：US11674924

申请日：2007-02-14

申请人： Lawrence Hudepohl ,  Darren Jones ,  Radhika Thekkath ,  Franz Treue

发明人： Lawrence Hudepohl ,  Darren Jones ,  Radhika Thekkath ,  Franz Treue

IPC分类号： G06F15/00

CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859

摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.

摘要翻译： 提供了中央处理单元（CPU）和协处理器之间的可配置协处理器接口。 协处理器接口具有用于将不同指令类型从CPU向协处理器顺序或并行传送到忙信号组的指令传送信号组，用于允许协处理器向CPU发信号通知其不能接收一个或多个 不同的指令类型和用于向协处理器指示并行传送的多个指令的相对执行顺序的指令顺序信号组。 此外，协处理器接口包括用于从CPU传输到协处理器的数据的分离的数据传输信号组，以及用于指示数据的相对顺序的数据顺序信号组（从协处理器传送到CPU） 如果无序转移）。 该接口还包括允许CPU和一个或多个协处理器之间的多个问题组的信号指定。

公开(公告)号：US07194599B2

公开(公告)日：2007-03-20

申请号：US11380925

申请日：2006-04-29

申请人： Lawrence H Hudepohl ,  Darren M Jones ,  Radhika Thekkath ,  Franz Treue

发明人： Lawrence H Hudepohl ,  Darren M Jones ,  Radhika Thekkath ,  Franz Treue

IPC分类号： G06F9/38

CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859

摘要： A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially or in parallel, a busy signal group, for allowing the coprocessor to signal the CPU that it cannot receive a transfer of one or more of the different instruction types, and an instruction order signal group for indicating to the coprocessor a relative execution order for multiple instructions that are transferred in parallel. In addition, the coprocessor interface includes separate data transfer signal groups for data being transferred from the CPU to the coprocessor, and for data being transferred from the coprocessor to the CPU, along with a data order signal group for indicating a relative order of data (if transferred out-of-order). The interface further includes signal designations which allow for multiple issue groups between the CPU and one or more coprocessors.