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58 条记录 (耗时 0.056 秒)

    Data streamer
    2.
    发明授权
    Data streamer 有权
    数据流

    公开(公告)号：US06434649B1

    公开(公告)日：2002-08-13

    申请号：US09173297

    申请日：1998-10-14

    申请人： David Baker ,  Christopher Basoglu ,  Benjamin Cutler ,  Gregorio Gervasio ,  Woobin Lee ,  Yatin Mundkur ,  Toru Nojiri ,  John O'Donnell ,  David Poole ,  Ashok Raman ,  Eric Rehm ,  Radhika Thekkath

    发明人： David Baker ,  Christopher Basoglu ,  Benjamin Cutler ,  Gregorio Gervasio ,  Woobin Lee ,  Yatin Mundkur ,  Toru Nojiri ,  John O'Donnell ,  David Poole ,  Ashok Raman ,  Eric Rehm ,  Radhika Thekkath

    IPC分类号： G06F1300

    CPC分类号： G06F13/30 ,  G06F13/1605

    摘要： In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.

    摘要翻译： 在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线 其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。 处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。 处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。内部存储器总线被配置为从预定数量接收地址和数据信息 的模块，包括内存和I / O设备。 内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。 收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

    Data transfer engine of a processor having a plurality of modules
    3.
    发明授权
    Data transfer engine of a processor having a plurality of modules 有权
    具有多个模块的处理器的数据传输引擎

    公开(公告)号：US07051123B1

    公开(公告)日：2006-05-23

    申请号：US09710192

    申请日：2000-11-10

    申请人： David Baker ,  Christopher Basoglu ,  Benjamin Cutler ,  Gregorio Gervasio ,  Woobin Lee ,  Yatin Mundkur ,  Toru Nojiri ,  John O'Donnell ,  Ashok Raman ,  Eric Rehm ,  Radhika Thekkath

    发明人： David Baker ,  Christopher Basoglu ,  Benjamin Cutler ,  Gregorio Gervasio ,  Woobin Lee ,  Yatin Mundkur ,  Toru Nojiri ,  John O'Donnell ,  Ashok Raman ,  Eric Rehm ,  Radhika Thekkath

    IPC分类号： G06F3/00

    CPC分类号： G06F13/30 ,  G06F13/1605

    摘要： In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus.An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.

    摘要翻译： 在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线 其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。 处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。 处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。 内部存储器总线被配置为从包括存储器和I / O设备的预定数量的模块接收地址和数据信息。 内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。 收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

    Data cache system
    4.
    发明授权
    Data cache system 失效

    公开(公告)号：US06560674B1

    公开(公告)日：2003-05-06

    申请号：US09172646

    申请日：1998-10-14

    申请人： Koji Hosogi ,  Gregorio Gervasio ,  Yatin Mundkur ,  Radhika Thekkath

    发明人： Koji Hosogi ,  Gregorio Gervasio ,  Yatin Mundkur ,  Radhika Thekkath

    IPC分类号： G06F1200

    CPC分类号： G06F12/0835 ,  G06F12/0833 ,  G06F12/0875

    摘要： An information processing system has a plurality of modules, including a processor, a main memory and a plurality of I/O devices. A data cache comprises a cache data memory which is coupled to the processor which provides data to the processor in response to a load operation and for writing data from the processor in response to a store operation. A refill controller is coupled to the cache data memory for controlling the operation of the data cache in accordance with a specifiable policy. An external access controller is coupled to the cache data memory. The external access controller is coupled to an external memory bus, such that the contents of the cache data memory are accessible for read and write operations in response to read and write requests issued by the modules in the information processing system.

    External trace synchronization via periodic sampling
    5.
    发明授权
    External trace synchronization via periodic sampling 有权
    通过定期采样进行外部跟踪同步

    公开(公告)号：US08185879B2

    公开(公告)日：2012-05-22

    申请号：US11557005

    申请日：2006-11-06

    申请人： Radhika Thekkath ,  Franz Treue ,  Ernest L. Edgar ,  Richard T. Leatherman

    发明人： Radhika Thekkath ,  Franz Treue ,  Ernest L. Edgar ,  Richard T. Leatherman

    IPC分类号： G06F9/44 ,  G06F9/45 ,  G06F11/00

    CPC分类号： G06F11/3636 ,  G06F11/3648 ,  G06F11/3656

    摘要： A method for tracing a multi-tasking embedded pipelined processor includes executing compiled code including trace controls. Tracing is initiated when the execution of the compiled code is initiated. Tracing is stopped when execution of the compiled code is completed. A trace record is formed during tracing. The trace record includes a processor mode indication, application space identity value and an instruction architecture set mode indication.

    摘要翻译： 用于跟踪多任务嵌入式流水线处理器的方法包括执行包括跟踪控制的编译代码。 执行编译代码时启动跟踪。 编译代码的执行完成后，跟踪停止。 在跟踪期间形成跟踪记录。 跟踪记录包括处理器模式指示，应用空间标识值和指令体系结构设置模式指示。

    Trace control from hardware and software
    7.
    发明授权
    Trace control from hardware and software 有权
    来自硬件和软件的跟踪控制

    公开(公告)号：US07644319B2

    公开(公告)日：2010-01-05

    申请号：US12187631

    申请日：2008-08-07

    申请人： Radhika Thekkath

    发明人： Radhika Thekkath

    IPC分类号： G06F11/00

    CPC分类号： G06F11/3636

    摘要： A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

    摘要翻译： 公开了一种用于程序计数器和数据跟踪的系统和方法。 本发明的跟踪机制能够提高对处理器核心的硬件和软件状态的可见性。

    Processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses
    8.
    发明申请
    Processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses 有权
    具有写入指令的处理器和将寄存器地址与存储器地址相关联的数据移动器引擎

    公开(公告)号：US20070174595A1

    公开(公告)日：2007-07-26

    申请号：US11336938

    申请日：2006-01-23

    申请人： Radhika Thekkath ,  Karagada Kishore ,  Vidya Rajagopalan

    发明人： Radhika Thekkath ,  Karagada Kishore ,  Vidya Rajagopalan

    IPC分类号： G06F9/44

    CPC分类号： G06F9/3004 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/383 ,  G06F9/384

    摘要： A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instruction. The read-tie, single write-tie, and dual write-tie instructions are used to associate software accessible register addresses with memory addresses. These associations effect the operation of the data mover engine such that, for the duration of the associations, the data mover engine routes data to and from associated memory addresses and the execution unit of the processor in response to instructions that specify moving data to and from the associated register addresses. The invention reduces the number of instructions and hardware overhead associated with implementing program loops in a RISC processor.

    摘要翻译： 具有数据移动器引擎的RISC处理器和将寄存器地址与存储器地址相关联的指令。 在一个实施例中，指令包括读取连接指令，单个写入指令，双重写入指令和解开指令。 读带，单写和双写指令用于将软件可访问寄存器地址与存储器地址相关联。 这些关联影响数据移动器引擎的操作，使得在关联的持续时间内，数据移动器引擎响应于指定移动数据到和从...移动数据的指令，将数据路由到相关联的存储器地址和处理器的执行单元 关联的寄存器地址。 本发明减少了与RISC处理器中实现程序循环相关联的指令数量和硬件开销。

    Dynamic selection of a compression algorithm for trace data
    9.
    发明申请
    Dynamic selection of a compression algorithm for trace data 有权
    动态选择跟踪数据的压缩算法

    公开(公告)号：US20060225050A1

    公开(公告)日：2006-10-05

    申请号：US11445518

    申请日：2006-06-02

    申请人： Radhika Thekkath

    发明人： Radhika Thekkath

    IPC分类号： G06F9/44

    CPC分类号： G06F11/364

    摘要： A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.

    摘要翻译： 公开了一种用于程序计数器和数据跟踪的系统和方法。 本发明的跟踪机制能够提高对处理器核心的硬件和软件状态的可见性。