公开(公告)号：US20060005084A1

公开(公告)日：2006-01-05

申请号：US10882813

申请日：2004-06-30

Applicant: Gilbert Neiger ,  Andrew Anderson ,  Steven Bennett ,  Jason Brandt ,  Erik Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Sanjoy Mondal ,  Rajesh Parthasarathy ,  Dion Rodgers ,  Lawrence Smith ,  Richard Uhlig

Inventor： Gilbert Neiger ,  Andrew Anderson ,  Steven Bennett ,  Jason Brandt ,  Erik Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Sanjoy Mondal ,  Rajesh Parthasarathy ,  Dion Rodgers ,  Lawrence Smith ,  Richard Uhlig

IPC: G06F11/00

CPC classification number: G06F9/45533 ,  G06F11/0712 ,  G06F11/0775 ,  G06F11/0787 ,  G06F11/0793

Abstract: In one embodiment, information pertaining to a first fault occurring during operation of a virtual machine (VM) is stored in a first field. A second fault is detected while delivering the first fault to the VM, and a determination is made as to whether the second fault is associated with a transition of control to a virtual machine monitor (VMM). If this determination is positive, information pertaining to the second fault is stored in a second field, and control is transitioned to the VMM.

Abstract translation: 在一个实施例中，关于在虚拟机（VM）的操作期间发生的第一故障的信息被存储在第一字段中。 在向VM提供第一故障时检测到第二故障，并且确定第二故障是否与对虚拟机监视器（VMM）的控制转换相关联。 如果该确定是肯定的，则关于第二故障的信息被存储在第二场中，并且控制被转换到VMM。

公开(公告)号：US20140032624A1

公开(公告)日：2014-01-30

申请号：US14042681

申请日：2013-09-30

Applicant: Ronen Zohar ,  Mark Seconi ,  Rajesh Parthasarathy ,  Srinivas Chennupaty ,  Mark Buxton ,  Chuck Desylva

Inventor： Ronen Zohar ,  Mark Seconi ,  Rajesh Parthasarathy ,  Srinivas Chennupaty ,  Mark Buxton ,  Chuck Desylva

IPC: G06F17/10

CPC classification number: G06F17/10 ,  G06F7/48 ,  G06F7/5443 ,  G06F9/3001

Abstract: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.

Abstract translation: 用于执行点积运算的方法，装置和程序装置。 在一个实施例中，一种装置包括执行第一指令的执行资源。 响应于第一指令，所述执行资源存储到存储位置，结果值等于至少两个操作数的点积。

公开(公告)号：US08423682B2

公开(公告)日：2013-04-16

申请号：US11323465

申请日：2005-12-30

Applicant: Sham M. Datta ,  Robert Greiner ,  Frank Binns ,  Keshavan Tiruvallur ,  Rajesh Parthasarathy ,  Madhavan Parthasarathy

Inventor： Sham M. Datta ,  Robert Greiner ,  Frank Binns ,  Keshavan Tiruvallur ,  Rajesh Parthasarathy ,  Madhavan Parthasarathy

IPC: G06F3/00 ,  G06F12/00 ,  G06F9/26 ,  G06F9/34

CPC classification number: G06F9/342 ,  G06F9/30174 ,  G06F12/0292 ,  G06F12/063 ,  G06F2212/206

Abstract: Apparatus and systems, as well as methods and articles, may operate to detect an input/output access operation associated with a configuration memory address and a first memory address bit size. The configuration memory address and associated configuration data may be combined into a packet having a second memory address bit size (e.g., 64 bits) greater than the first memory address bit size (e.g., 32 bits). The packet may be used to establish compatibility for legacy operating systems that attempt to communicate with peripheral component interconnect (PCI) interface-based peripherals, and similar platform devices, that have been integrated into the same package as the processor.

Abstract translation: 装置和系统以及方法和物品可以操作以检测与配置存储器地址和第一存储器地址位大小相关联的输入/输出访问操作。 配置存储器地址和相关联的配置数据可以被组合成具有大于第一存储器地址位大小（例如，32位）的第二存储器地址位大小（例如，64位）的分组。 该分组可以用于为尝试与外围组件互连（PCI）接口的外围设备以及已经集成到与处理器相同的封装中的类似的平台设备进行通信的传统操作系统建立兼容性。

公开(公告)号：US08103816B2

公开(公告)日：2012-01-24

申请号：US12290208

申请日：2008-10-28

Applicant: Keshavan Tiruvallur ,  Rajesh Parthasarathy ,  James B. Crossland ,  Shivnanda Kaushik ,  Luke Hood

Inventor： Keshavan Tiruvallur ,  Rajesh Parthasarathy ,  James B. Crossland ,  Shivnanda Kaushik ,  Luke Hood

IPC: G06F13/24 ,  G06F13/26

CPC classification number: G06F13/24

Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

Abstract translation: 一种在计算机系统内实现高效中断通信的技术。 在一个实施例中，高级可编程中断控制器（APIC）通过使用各种接口指令或操作的APIC接口寄存器内的一组位进行接口，而不使用存储器映射的输入/输出（MMIO）。

公开(公告)号：US20100106875A1

公开(公告)日：2010-04-29

申请号：US12290208

申请日：2008-10-28

Applicant: Keshavan Tiruvallur ,  Rajesh Parthasarathy ,  James B. Crossland ,  Shivnanda Kaushik ,  Luke Hood

Inventor： Keshavan Tiruvallur ,  Rajesh Parthasarathy ,  James B. Crossland ,  Shivnanda Kaushik ,  Luke Hood

IPC: G06F13/24

CPC classification number: G06F13/24

Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

Abstract translation: 一种在计算机系统内实现高效中断通信的技术。 在一个实施例中，高级可编程中断控制器（APIC）通过使用各种接口指令或操作的APIC接口寄存器内的一组位进行接口，而不使用存储器映射的输入/输出（MMIO）。

公开(公告)号：US20070174587A1

公开(公告)日：2007-07-26

申请号：US11323465

申请日：2005-12-30

Applicant: Sham Datta ,  Robert Greiner ,  Frank Binns ,  Keshavan Tiruvallur ,  Rajesh Parthasarathy ,  Madhavan Parthasarathy

Inventor： Sham Datta ,  Robert Greiner ,  Frank Binns ,  Keshavan Tiruvallur ,  Rajesh Parthasarathy ,  Madhavan Parthasarathy

IPC: G06F15/00

CPC classification number: G06F9/342 ,  G06F9/30174 ,  G06F12/0292 ,  G06F12/063 ,  G06F2212/206

Abstract: Apparatus and systems, as well as methods and articles, may operate to detect an input/output access operation associated with a configuration memory address and a first memory address bit size. The configuration memory address and associated configuration data may be combined into a packet having a second memory address bit size (e.g., 64 bits) greater than the first memory address bit size (e.g., 32 bits). The packet may be used to establish compatibility for legacy operating systems that attempt to communicate with peripheral component interconnect (PCI) interface-based peripherals, and similar platform devices, that have been integrated into the same package as the processor.

Abstract translation: 装置和系统以及方法和物品可以操作以检测与配置存储器地址和第一存储器地址位大小相关联的输入/输出访问操作。 配置存储器地址和相关联的配置数据可以被组合成具有大于第一存储器地址位大小（例如，32位）的第二存储器地址位大小（例如，64位）的分组。 该分组可以用于为尝试与外围组件互连（PCI）接口的外围设备以及已经集成到与处理器相同的封装中的类似的平台设备进行通信的传统操作系统建立兼容性。

公开(公告)号：US08312198B2

公开(公告)日：2012-11-13

申请号：US13356999

申请日：2012-01-24

Applicant: Keshavan Tiruvallur ,  Rajesh Parthasarathy ,  James B. Crossland ,  Shivnandan Kaushik ,  Luke Hood

Inventor： Keshavan Tiruvallur ,  Rajesh Parthasarathy ,  James B. Crossland ,  Shivnandan Kaushik ,  Luke Hood

IPC: G06F13/24 ,  G06F13/26

CPC classification number: G06F13/24

Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APlC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

Abstract translation: 一种在计算机系统内实现高效中断通信的技术。 在一个实施例中，高级可编程中断控制器（AP1C）通过使用各种接口指令或操作的APIC接口寄存器内的一组位来进行接口，而不使用存储器映射的输入/输出（MMIO）。