Status bit controlled HDLC accelerator
    1.
    发明授权
    Status bit controlled HDLC accelerator 失效
    状态位控制HDLC加速器

    公开(公告)号:US5638370A

    公开(公告)日:1997-06-10

    申请号:US365356

    申请日:1994-12-28

    CPC classification number: H04L1/0057 H04L29/06 H04L69/324

    Abstract: A status bit controlled HDLC accelerator comprises a fully programmable CRC generation circuit, a partial data packet formatting/unformatting capability and a dual-mode register set. The HDLC accelerator includes a set of registers that can be written to and read from directly via a bus interface circuit. Moreover, these registers may be written to and read from at any time so that the state of the HDLC accelerator during a formatting or unformatting operation may be stored in mid-operation. The HDLC accelerator further includes a CRC generation circuit that can perform various checkword generation functions in response to a programmable CRC generator polynomial. In addition, programmable counters within the HDLC accelerator allow partial data packets to be processed which thereby enables formatting and unformatting data packets of all valid bit enumerations.

    Abstract translation: 状态位控制的HDLC加速器包括完全可编程的CRC生成电路,部分数据分组格式化/非格式化能力以及双模式寄存器组。 HDLC加速器包括一组可以通过总线接口电路直接写入和读取的寄存器。 此外,这些寄存器可以在任何时刻被写入和读取,使得格式化或非格式化操作期间的HDLC加速器的状态可以被存储在中间操作中。 HDLC加速器还包括CRC生成电路,其可以响应于可编程CRC生成多项式来执行各种复制词生成功能。 此外,HDLC加速器内的可编程计数器允许处理部分数据包,从而可以格式化和取消格式化所有有效位枚举的数据包。

    Method and apparatus for performing select operations
    8.
    发明申请
    Method and apparatus for performing select operations 审中-公开
    用于执行选择操作的方法和装置

    公开(公告)号:US20080077772A1

    公开(公告)日:2008-03-27

    申请号:US11526065

    申请日:2006-09-22

    Abstract: A method and apparatus for including in a processor instructions for performing select operations on packed or unpacked data. In one embodiment, a processor is coupled to a memory. The memory has stored therein first packed data in a source operand and a second packed data in a destination operand. The processor selects the first packed data if the control bit for the source operand is set to “1” and stores the data into the destination operand. Otherwise, the processor keeps the data in the destination operand. The final value of the destination operand is stored in memory.

    Abstract translation: 一种用于在处理器中包括用于对打包或未打包的数据执行选择操作的指令的方法和装置。 在一个实施例中,处理器耦合到存储器。 存储器中存储有源操作数中的第一打包数据和目的地操作数中的第二打包数据。 如果源操作数的控制位设置为“1”,则处理器选择第一打包数据,并将数据存储到目标操作数中。 否则,处理器将数据保存在目标操作数中。 目标操作数的最终值存储在内存中。

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