公开(公告)号：US5473758A

公开(公告)日：1995-12-05

申请号：US938911

申请日：1992-08-31

Applicant: Ray Allen ,  Sumit Mitra ,  Rodney Drake

Inventor： Ray Allen ,  Sumit Mitra ,  Rodney Drake

IPC: G11C16/10 ,  G06F15/02

CPC classification number: G11C16/102

Abstract: A microcontroller and associated EPROM program memory are fabricated in a single semiconductor chip. The microcontroller device is adapted to be programmed using digital command words or other bit patterns applied as inputs after installation of the device in circuit with a system to be controlled by the device, and to have its programming pins isolated from the system to avoid effects on system operation while the programming is taking place. The in-circuit programming uses considerably less than the total number of input/output (I/O) pins of the device, which in total are fewer than the number of bits in a command word. This is achieved with a serial/parallel programming interface between the pins and the program memory, and by applying the data in serial fashion to the interface where it is latched and loaded in parallel in the memory. Input data to the device may alternatively be entered in parallel to the interface in bytes of width less than the total number of I/O pins of the device.

Abstract translation: 在单个半导体芯片中制造微控制器和相关联的EPROM程序存储器。 微控制器设备适于在使用要由设备控制的系统安装设备的电路中的数字命令字或其他位模式中使用数字命令字或其他位模式进行编程，并将其编程引脚与系统隔离以避免对 系统运行时正在进行编程。 在线编程使用量远低于设备的输入/输出（I / O）引脚总数，总共少于命令字中的位数。 这是通过引脚和程序存储器之间的串行/并行编程接口实现的，并且通过将数据以串行方式应用于其被锁存并且并行加载到存储器中的接口来实现。 输入到设备的数据可以替代地以与字节相同的字节并行输入，该字节的宽度小于设备的I / O引脚的总数。

公开(公告)号：US5351216A

公开(公告)日：1994-09-27

申请号：US26908

申请日：1993-03-05

Applicant: Tom Salt ,  Rodney Drake ,  Ray Allen

Inventor： Tom Salt ,  Rodney Drake ,  Ray Allen

IPC: G05B19/042 ,  G06F11/14 ,  G11C16/22 ,  G06K5/00

CPC classification number: G05B19/0428 ,  G06F11/1402 ,  G11C16/22 ,  G05B2219/23215 ,  G05B2219/23345 ,  G05B2219/25301

Abstract: A single chip, semiconductor microcontroller device is adapted to control an aspect of the operation of an external system. The device includes a CPU, program memory for storing instructions to be selectively executed by the CPU to perform the control functions, and peripheral EEPROM data memory adapted to be written to for storing selected data in selected ones of a multiplicity of addresses of the data memory and for selective retrieval of the stored dam by the CPU within its control function. Internal logic in the device is implemented to abort a write operation in progress on the EEPROM data memory upon occurrence of an asynchronous reset of the device. An error flag is set by the logic to indicate that the write operation is being aborted, and the data that was partially written to the EEPROM memory at the time the write operation was aborted is held intact.

Abstract translation: 单芯片半导体微控制器装置适于控制外部系统的操作的一个方面。 该装置包括CPU，用于存储由CPU选择性地执行以执行控制功能的指令的程序存储器，以及适于被写入以便将选择的数据存储在数据存储器的多个地址中的选定数据中的外围EEPROM数据存储器 并且用于在其控制功能内由CPU选择性地检索存储的水坝。 器件的内部逻辑被实现为在器件的异步复位发生时中止EEPROM数据存储器上正在进行的写入操作。 由逻辑设置错误标志以指示写入操作正在中止，并且在写入操作中止时部分写入EEPROM存储器的数据保持不变。

公开(公告)号：US20170270496A1

公开(公告)日：2017-09-21

申请号：US15602058

申请日：2017-05-22

Applicant: Dyron Clower ,  John Templer ,  La Shonna Sharp ,  Aaron Calipari ,  Michael Ring ,  Michael Serrette ,  Nickolas Ledford ,  Lawrence Dugger ,  Rodney Drake ,  Diana Hayes

Inventor： Dyron Clower ,  John Templer ,  La Shonna Sharp ,  Aaron Calipari ,  Michael Ring ,  Michael Serrette ,  Nickolas Ledford ,  Lawrence Dugger ,  Rodney Drake ,  Diana Hayes

IPC: G06Q20/10

CPC classification number: G06Q20/1085 ,  G06Q20/042 ,  G06Q20/3223 ,  G06Q20/40145 ,  G06Q20/4016 ,  G06Q20/405 ,  G06Q40/02

Abstract: A real-time system and method for determining whether to invoke a fraud alert notification to a bank concerning an account holder or an item issuer following an interim determination that the account holder or item issuer has participated in a fraudulent transaction. An interim determination is updated based in part on bank transaction data received following the interim determination.

公开(公告)号：US06230275B1

公开(公告)日：2001-05-08

申请号：US09232053

申请日：1999-01-15

Applicant: Joseph W. Triece ,  Rodney Drake ,  Igor Wojewoda

Inventor： Joseph W. Triece ,  Rodney Drake ,  Igor Wojewoda

IPC: G06F126

CPC classification number: G11C5/14 ,  G11C7/1045 ,  H03K19/0016

Abstract: A system for powering down configuration circuits to minimize power consumption has at least one first configuration circuit for configuring a peripheral module. A second configuration circuit is coupled to the peripheral module and to the at least one first configuration circuit. The second configuration circuit is used for enabling and disabling the peripheral module. The second configuration circuit is further used to power down the at least one first configuration circuit to minimize current consumption of the at least one first configuration circuit when the peripheral module is disabled.

Abstract translation: 用于断电配置电路以最小化功耗的系统具有用于配置外围模块的至少一个第一配置电路。 第二配置电路耦合到外围模块和至少一个第一配置电路。 第二个配置电路用于启用和禁用外围模块。 当外围模块被禁用时，第二配置电路还用于断电至少一个第一配置电路以最小化至少一个第一配置电路的电流消耗。

公开(公告)号：US5861861A

公开(公告)日：1999-01-19

申请号：US671575

申请日：1996-06-28

Applicant: James B. Nolan ,  Scott Ellison ,  Brian Boles ,  Rodney Drake ,  Russell E. Cooper

Inventor： James B. Nolan ,  Scott Ellison ,  Brian Boles ,  Rodney Drake ,  Russell E. Cooper

IPC: G02F1/133 ,  G06F3/147 ,  G09G3/00 ,  G09G3/18 ,  G09G3/36 ,  G09G5/00 ,  H02M3/07

CPC classification number: H02M3/07 ,  G06F3/147 ,  G09G3/18 ,  G09G3/006 ,  G09G3/3696 ,  G09G5/001

Abstract: Apparatus for providing multiple of discrete voltage levels to drive a liquid crystal display (LCD) from an LCD module on board a microcontroller chip includes a charge pump with a switched-capacitor that develops the discrete voltages as multiples of the value of a base voltage that remains substantially without change irrespective of change in the supply voltage. A switched-capacitor charging circuit selectively charges a capacitor to produce successive additive charges individually retrievable from the capacitor. An LCD drive selectively transmits the discrete voltage levels to activate the LCD according to status of an external system under the control of the microcontroller. Voltage losses that may occur during the switched-capacitor charging are compensated to maintain the levels of the discrete voltages free of decay. Compensation is achieved by overcharging the capacitor by an amount substantially equivalent to the amount of voltage loss on the capacitor, using active feedback obtained from monitoring the charge on the capacitor.

Abstract translation: 用于提供多个离散电压电平以从微控制器芯片上的LCD模块驱动液晶显示器（LCD）的装置包括具有开关电容器的电荷泵，其将离散电压开发为基本电压值的倍数 无论电源电压的变化如何，均保持基本无变化。 开关电容器充电电路选择性地对电容器充电以产生可从电容器单独检索的连续的附加电荷。 LCD驱动器根据微控制器的控制，根据外部系统的状态选择性地发送离散电压电平以激活LCD。 在开关电容器充电期间可能发生的电压损耗被补偿以保持离散电压的电平没有衰减。 通过使用从监视电容器上的电荷获得的有效反馈，使电容器过充电达到与电容器上的电压损失量相当的量。

公开(公告)号：US5469557A

公开(公告)日：1995-11-21

申请号：US26967

申请日：1993-03-05

Applicant: Tom Salt ,  Rodney Drake

Inventor： Tom Salt ,  Rodney Drake

IPC: G11C8/20 ,  G11C16/22 ,  G06F12/14 ,  H04L9/00

CPC classification number: G11C8/20 ,  G11C16/22

Abstract: A semiconductor microcontroller device is adapted to control the operation of an external system. The device includes a CPU, program memory for storing instructions to be executed by the CPU to perform its control functions, and data memory for storing data for selective retrieval by the CPU. The contents of either memory are code protected by an EEPROM fuse, and are automatically erased if the code protect state of the EEPROM fuse is sought to be reset, and the EEPROM fuse is reset only after the erasure of the memory contents.

Abstract translation: 半导体微控制器装置适于控制外部系统的操作。 该设备包括CPU，用于存储要由CPU执行以执行其控制功能的指令的程序存储器，以及用于存储用于CPU选择性检索的数据的数据存储器。 任何一个存储器的内容均由EEPROM保险丝进行代码保护，如果要求复位EEPROM保险丝的代码保护状态，并且只有擦除存储器内容之后EEPROM保险丝才会被复位。

公开(公告)号：US06463544B2

公开(公告)日：2002-10-08

申请号：US09850214

申请日：2001-05-07

Applicant: Joseph W. Triece ,  Rodney Drake ,  Igor Wojewoda

Inventor： Joseph W. Triece ,  Rodney Drake ,  Igor Wojewoda

IPC: G06F126

CPC classification number: G11C5/14 ,  G11C7/1045 ,  H03K19/0016

Abstract: A system for powering down configuration circuits to minimize power consumption has at least one first configuration circuit for configuring a peripheral module. A second configuration circuit is coupled to the peripheral module and to the at least one first configuration circuit. The second configuration circuit is used for enabling and disabling the peripheral module. The second configuration circuit is further used to power down the at least one first configuration circuit to minimize current consumption of the at least one first configuration circuit when the peripheral module is disabled.

Abstract translation: 用于断电配置电路以最小化功耗的系统具有用于配置外围模块的至少一个第一配置电路。 第二配置电路耦合到外围模块和至少一个第一配置电路。 第二个配置电路用于启用和禁用外围模块。 当外围模块被禁用时，第二配置电路还用于断电至少一个第一配置电路以最小化至少一个第一配置电路的电流消耗。