公开(公告)号：US20070299679A1

公开(公告)日：2007-12-27

申请号：US11508612

申请日：2006-08-23

Applicant: Amit Sudan ,  Manbhawan Prasad ,  Maninderjit Singh ,  Rohit Bhatia ,  Sandeep Sadanandan

Inventor： Amit Sudan ,  Manbhawan Prasad ,  Maninderjit Singh ,  Rohit Bhatia ,  Sandeep Sadanandan

IPC: G06Q10/00 ,  G06Q30/00

CPC classification number: G06Q30/00 ,  G06Q10/00

Abstract: A business system interface for accessing data from a Line-of-Business (LOB) system from within an information worker productivity (IWP) application is provided. The business system interface includes an embedded business system user interface contained within a user interface of the IWP application. Also included, is a business data access component that can retrieve data from the LOB system and provide the retrieved data to the embedded business system user interface. The embedded business system user interface and the business data access component contain at least some managed code components.

Abstract translation: 提供了一种用于从信息工作者生产率（IWP）应用程序中访问来自业务线（LOB）系统的数据的业务系统接口。 业务系统接口包括包含在IWP应用的用户界面内的嵌入式业务系统用户界面。 还包括一个业务数据访问组件，可以从LOB系统检索数据，并将检索到的数据提供给嵌入式业务系统用户界面。 嵌入式业务系统用户界面和业务数据访问组件至少包含一些托管代码组件。

公开(公告)号：US06910122B1

公开(公告)日：2005-06-21

申请号：US09507204

申请日：2000-02-18

Applicant: Stephen L. Bass ,  Rohit Bhatia

Inventor： Stephen L. Bass ,  Rohit Bhatia

IPC: G06F9/38 ,  G06F15/00

CPC classification number: G06F9/3869 ,  G06F9/3824 ,  G06F9/3867

Abstract: Methods and apparatus for stalling a pipeline, which methods and apparatus allow data in speed critical pipeline stages to propagate through additional stages of the pipeline. The data is then “caught” and stored in a deferred stall register as it is output from a downstream pipeline stage X. Finally, the data is output from the deferred stall register in a way that it masks the regular output of the pipeline stage X. In this manner, there is no need to store stalled data in a speed critical pipeline stage. Rather, the data can slip ahead, be saved, and be output at an appropriate time such that it appears that the data was stalled in the pipeline stage in which it existed at the time a stall was initiated.

Abstract translation: 用于停止管道的方法和装置，哪些方法和装置允许速度关键流水线阶段的数据通过管道的附加级传播。 然后将数据“捕获”并存储在从下游流水线阶段X输出的延迟停顿寄存器中。最后，数据以延迟停顿寄存器的方式从屏蔽流水线级X的常规输出 以这种方式，不需要在速度关键的流水线阶段存储停滞的数据。 相反，数据可以向前滑动，被保存并在适当的时间输出，使得数据在发起失速时存在的流水线阶段停止。

公开(公告)号：US20050091652A1

公开(公告)日：2005-04-28

申请号：US10695267

申请日：2003-10-28

Applicant: Jonathan Ross ,  Dale Morris ,  Donald Soltis ,  Rohit Bhatia ,  Eric Delano

Inventor： Jonathan Ross ,  Dale Morris ,  Donald Soltis ,  Rohit Bhatia ,  Eric Delano

IPC: G06F9/455

CPC classification number: G06F9/45533

Abstract: Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.

Abstract translation: 虚拟机监视器的操作和实现通过添加到处理器架构的特征中的容易实现的特征和扩展的数量来实现。 这些特征，其中一个或多个在本发明的各种实施例中使用，包括提供用于在不中断的情况下在虚拟化模式和非虚拟化模式之间转换的手段的vmsw指令，虚拟化故障， 尝试执行特权指令的虚拟化模式中的优先级0例程，以及将虚拟地址空间划分为虚拟化地址空间和非虚拟化地址空间的灵活的最高实现地址机制。

公开(公告)号：US5313413A

公开(公告)日：1994-05-17

申请号：US027934

申请日：1993-03-08

Applicant: Rohit Bhatia ,  Masaru Furuta

Inventor： Rohit Bhatia ,  Masaru Furuta

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/132 ,  G02F1/01 ,  G02F1/065 ,  G02F1/35 ,  G02F1/355 ,  G02F1/361 ,  G06F9/38 ,  G06F17/14 ,  G06F15/00

CPC classification number: G02B6/1221 ,  G02B6/132 ,  G02F1/065 ,  G06F17/142 ,  G06F9/3824

Abstract: A Quasi Radix-16 Butterfly comprises an radix-4 butterfly processor and on-board memory with external memory addressing changes from a conventional radix-4 butterfly processor. On-chip cache memory is included to store data outputs of the radix-4 butterfly processor for application as data inputs to the radix-4 butterfly processor in a second series of butterfly operations to implement high-speed processing that is maximally execution-bound.

Abstract translation: 准基数16蝴蝶包括一个基数4蝶形处理器和板载存储器，外部存储器用于寻址传统的基4蝶形处理器的更改。 包括片上高速缓存存储器，用于存储基数-4蝶形处理器的数据输出，用于在第二系列蝶式运算中作为基数-4蝶形处理器的数据输入，以实现最大限度执行的高速处理。

公开(公告)号：US20140181484A1

公开(公告)日：2014-06-26

申请号：US13725934

申请日：2012-12-21

Applicant: James Callister ,  Don Soltis ,  Rohit Bhatia ,  Ramkumar Srinivasan ,  Steven Bostian ,  Richard M. Blumberg

Inventor： James Callister ,  Don Soltis ,  Rohit Bhatia ,  Ramkumar Srinivasan ,  Steven Bostian ,  Richard M. Blumberg

IPC: G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/4881

Abstract: According to one embodiment, a processor includes an execution pipeline for executing a plurality of threads, including a first thread and a second thread. The processor further includes a multi-thread controller (MTC) coupled to the execution pipeline to determine whether to switch threads between the first and second thread based on a thread switch policy that is selected from a list of thread switch policies based on unfairness levels of the first and second thread, and in response to determining to switch threads, to switch from executing the first thread to executing the second thread.

Abstract translation: 根据一个实施例，处理器包括用于执行包括第一线程和第二线程的多个线程的执行流水线。 处理器还包括耦合到执行流水线的多线程控制器（MTC），以基于从线程切换策略列表中选择的线程切换策略来确定是否在第一和第二线程之间切换线程，所述线程切换策略基于线程切换策略的列表， 第一线程和第二线程，并且响应于确定切换线程，从执行第一线程切换到执行第二线程。

公开(公告)号：US20130326582A1

公开(公告)日：2013-12-05

申请号：US13489165

申请日：2012-06-05

Applicant: Michael J. Kruzeniski ,  Joseph B. Tobens ,  Jon Bell ,  William Scott Stauber ,  Rohit Bhatia ,  Ram Pattabhi Papatla ,  Daniel Escapa

Inventor： Michael J. Kruzeniski ,  Joseph B. Tobens ,  Jon Bell ,  William Scott Stauber ,  Rohit Bhatia ,  Ram Pattabhi Papatla ,  Daniel Escapa

IPC: G06F21/00

CPC classification number: G06F3/04883 ,  G06F21/604 ,  G06F21/6209 ,  G06F2221/2149

Abstract: A note-capture application is disclosed that allows notes to be displayed on the lock screen. In one embodiment, a note-capture application can be invoked when a mobile device is in an above-lock state. Note data can be captured using the note-capture application, and the captured data can be persistently displayed on the lock screen. A user can perform a unique gesture from the lock screen to invoke the note-capture application. In another embodiment, multiple input modes can be available for note data capture. For example, voice data, text data, camera data, etc. can all be used to capture notes for display on the lock screen.

Abstract translation: 公开了一种允许在锁屏上显示笔记的记录捕获应用程序。 在一个实施例中，当移动设备处于上述锁定状态时，可以调用音符捕获应用。 记录数据可以使用记录捕获应用程序进行捕获，捕获的数据可以持续显示在锁定屏幕上。 用户可以从锁定屏幕执行唯一的手势来调用音符捕获应用程序。 在另一个实施例中，多个输入模式可用于笔记数据捕获。 例如，语音数据，文本数据，相机数据等都可以用于捕获在锁屏幕上显示的笔记。

公开(公告)号：US20130275787A1

公开(公告)日：2013-10-17

申请号：US13913864

申请日：2013-06-10

Applicant: Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

Inventor： Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203

Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

Abstract translation: 公开了减少处理器的步进负载的方法和装置。 方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并将执行限制到指令的子集 号码来控制执行期间的电量。 一些实施例还可以创建人为活动以为处理器提供最小功率层。 装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑 的执行期间要处理的指令。

公开(公告)号：US20120023036A1

公开(公告)日：2012-01-26

申请号：US13190655

申请日：2011-07-26

Applicant: MICHAEL SCHMANSKE ,  Maneesh Deshpande ,  Rohit Bhatia ,  Yidong Ding ,  Pankaj Khandelwal

Inventor： MICHAEL SCHMANSKE ,  Maneesh Deshpande ,  Rohit Bhatia ,  Yidong Ding ,  Pankaj Khandelwal

IPC: G06Q40/00

CPC classification number: G06Q40/04 ,  G06Q40/06

Abstract: An exemplary aspect comprises receiving data related to an underlying asset; calculating values corresponding to near-term implied volatility and realized volatility for the underlying asset; and transmitting data sufficient to describe an index based on a difference between the values corresponding to the near-term implied volatility and the realized volatility for the underlying asset. Another exemplary aspect comprises receiving electronic data related to an underlying asset; calculating data sufficient to describe a plurality of call options and a plurality of put options related to the underlying asset and written on a first settlement date; crediting an account with proceeds from selling the call and put options; and debiting the account to settle one or more of the options that are in-the-money on a second settlement date. Other aspects are apparent from the description and claims.

Abstract translation: 示例性方面包括接收与标的资产相关的数据; 计算相应资产的近期隐含波动率和实现波动率的值; 并且基于与短期隐含波动率相对应的值与标的资产的实现波动率之间的差异来传送足以描述指数的数据。 另一示例性方面包括接收与标的资产相关的电子数据; 计算足以描述多个看涨期权的数据和与相关资产相关并在第一结算日期写入的多个看跌期权; 记入销售电话和放置期权的收益; 并借记帐户以在第二个结算日期结算一个或多个在货币中的期权。 从描述和权利要求中，其它方面是显而易见的。

公开(公告)号：US20090070607A1

公开(公告)日：2009-03-12

申请号：US11900316

申请日：2007-09-11

Applicant: Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

Inventor： Kevin Safford ,  Rohit Bhatia ,  Chris Bostak ,  Richard Blumberg ,  Blaine Stackhouse ,  Steve Undy

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203

Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.

Abstract translation: 公开了减少处理器的步进负载的方法和装置。 方法实施例包括检查要由处理器处理的多个指令以确定其具有的指令的类型，基于指令的类型在执行周期中计算功耗，并将执行限制到指令的子集 号码来控制执行期间的电量。 一些实施例还可以创建人为活动以为处理器提供最小功率层。 装置实施例包括用于确定输入指令流中的指令类型的指令类型确定逻辑，用于计算与在执行周期中处理多个指令相关联的功耗的功率计算器，以及通过限制数量来控制功耗的指令限制逻辑 的执行期间要处理的指令。

公开(公告)号：US20060259907A1

公开(公告)日：2006-11-16

申请号：US11125859

申请日：2005-05-10

Applicant: Rohit Bhatia ,  Don Soltis

Inventor： Rohit Bhatia ,  Don Soltis

IPC: G06F9/46

CPC classification number: G06F9/526

Abstract: Systems and methods of sharing processing resources in a multi-threading environment are disclosed. An exemplary method may include allocating a lock value for a resource lock, the lock value corresponding to a state of the resource lock. A first thread may yield at least a portion of the processing resources for another thread. The resource lock may be acquired for the first thread if the lock value indicates the resource lock is available.

Abstract translation: 公开了在多线程环境中共享处理资源的系统和方法。 示例性方法可以包括为资源锁定分配锁定值，所述锁定值对应于所述资源锁定的状态。 第一个线程可以产生另一个线程的处理资源的至少一部分。 如果锁定值指示资源锁可用，则可以为第一线程获取资源锁。