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    Processor-architecture for facilitating a virtual machine monitor
    1.
    发明申请
    Processor-architecture for facilitating a virtual machine monitor 失效
    处理器架构，便于虚拟机监控

    公开(公告)号：US20050091652A1

    公开(公告)日：2005-04-28

    申请号：US10695267

    申请日：2003-10-28

    申请人： Jonathan Ross ,  Dale Morris ,  Donald Soltis ,  Rohit Bhatia ,  Eric Delano

    发明人： Jonathan Ross ,  Dale Morris ,  Donald Soltis ,  Rohit Bhatia ,  Eric Delano

    IPC分类号： G06F9/455

    CPC分类号： G06F9/45533

    摘要： Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.

    摘要翻译： 虚拟机监视器的操作和实现通过添加到处理器架构的特征中的容易实现的特征和扩展的数量来实现。 这些特征，其中一个或多个在本发明的各种实施例中使用，包括提供用于在不中断的情况下在虚拟化模式和非虚拟化模式之间转换的手段的vmsw指令，虚拟化故障， 尝试执行特权指令的虚拟化模式中的优先级0例程，以及将虚拟地址空间划分为虚拟化地址空间和非虚拟化地址空间的灵活的最高实现地址机制。

    Processor-architecture for facilitating a virtual machine monitor
    2.
    发明授权
    Processor-architecture for facilitating a virtual machine monitor 失效
    处理器架构，便于虚拟机监控

    公开(公告)号：US07421689B2

    公开(公告)日：2008-09-02

    申请号：US10695267

    申请日：2003-10-28

    申请人： Jonathan K. Ross ,  Dale Morris ,  Donald C. Soltis, Jr. ,  Rohit Bhatia ,  Eric Delano

    发明人： Jonathan K. Ross ,  Dale Morris ,  Donald C. Soltis, Jr. ,  Rohit Bhatia ,  Eric Delano

    IPC分类号： G06F9/455

    CPC分类号： G06F9/45533

    摘要： Virtual-machine-monitor operation and implementation is facilitated by number of easily implemented features and extensions added to the features of a processor architecture. These features, one or more of which are used in various embodiments of the present invention, include a vmsw instruction that provides a means for transitioning between virtualization mode and non-virtualization mode without an interruption, a virtualization fault that faults on an attempt by a priority-0 routine in virtualization mode attempting to execute a privileged instruction, and a flexible highest-implemented-address mechanism to partition virtual address space into a virtualization address space and a non-virtualization address space.

    摘要翻译： 虚拟机监视器的操作和实现通过添加到处理器架构的特征中的容易实现的特征和扩展的数量来实现。 这些特征，其中一个或多个在本发明的各种实施例中使用，包括提供用于在不中断的情况下在虚拟化模式和非虚拟化模式之间转换的手段的vmsw指令，虚拟化故障， 尝试执行特权指令的虚拟化模式中的优先级0例程，以及将虚拟地址空间划分为虚拟化地址空间和非虚拟化地址空间的灵活的最高实现地址机制。

    Privileged resource access
    3.
    发明申请
    Privileged resource access 审中-公开
    特权资源访问

    公开(公告)号：US20060064528A1

    公开(公告)日：2006-03-23

    申请号：US10944266

    申请日：2004-09-17

    申请人： Donald Soltis, ,  Dale Morris

    发明人： Donald Soltis, ,  Dale Morris

    IPC分类号： G06F13/24

    CPC分类号： G06F13/24

    摘要： At least one entry in an original interrupt vector table is replaced with an instruction set to handle access to a privileged resource. An operating system privilege level is modified to one or more resources. Subsequent access to the privileged resource causes an interrupt. Processing of the interrupt is directed to the instruction set to handle access to the privileged resource.

    摘要翻译： 原始中断向量表中的至少一个条目被替换为处理对特权资源的访问的指令集。 操作系统权限级别被修改为一个或多个资源。 对特权资源的后续访问会导致中断。 中断的处理针对指令集来处理对特权资源的访问。

    Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes
    6.
    发明申请
    Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes 失效
    具有用于分别存储用于多个处理器节点的TLB击落数据的多个存储器位置的多处理器系统

    公开(公告)号：US20060026359A1

    公开(公告)日：2006-02-02

    申请号：US10903200

    申请日：2004-07-30

    申请人： Jonathan Ross ,  Dale Morris

    发明人： Jonathan Ross ,  Dale Morris

    IPC分类号： G06F12/00 ,  G06F12/10

    CPC分类号： G06F12/1027 ,  G06F2212/682

    摘要： The present invention provides a multiprocessor system and method in which plural memory locations are used for storing TLB-shootdown data respectively for plural processors. In contrast to systems in which a single area of memory serves for all processors' TLB-shootdown data, different processors can describe the memory they want to free concurrently. Thus, concurrent TLB-shootdown request are less likely to result in performance-limiting TLB-shootdown contentions that have previously constrained the scaleability of multiprocessor systems.

    摘要翻译： 本发明提供一种多处理器系统和方法，其中使用多个存储器位置来分别存储用于多个处理器的TLB击倒数据。 与其中单个存储器区域用于所有处理器的TLB击倒数据的系统相反，不同的处理器可以描述他们想要同时释放的存储器。 因此，并发的TLB-downdown请求不太可能导致先前限制多处理器系统可扩展性的性能限制TLB击倒争用。

    Multiprocessor system with interactive synchronization of local clocks
    7.
    发明申请
    Multiprocessor system with interactive synchronization of local clocks 有权
    具有本地时钟交互式同步的多处理器系统

    公开(公告)号：US20050033947A1

    公开(公告)日：2005-02-10

    申请号：US10638696

    申请日：2003-08-08

    申请人： Dale Morris ,  Jonathan Ross

    发明人： Dale Morris ,  Jonathan Ross

    IPC分类号： G06F1/12 ,  G06F1/14 ,  G06F9/00 ,  H04J3/06

    CPC分类号： G06F1/14 ,  H04J3/0638

    摘要： A multiprocessor computer system comprises multiple data processors, each with an internal clock for providing time stamps to application software. The processors take turns as synchronization masters. The present master transmits a “request” time stamp (indicating the time of transmission according to the local clock) to the other (“slave”) processors. Each slave processor responds by returning a “response” time stamp (indicating the time of transmission of the response according to the local slave clock) of its own along with the received request time stamp. The master calculates clock adjustment values from the time of receipt of the responses and the included time stamps. This allows asynchronous clocks to be synchronized so that application time stamps can be validly compared across processors.

    摘要翻译： 多处理器计算机系统包括多个数据处理器，每个数据处理器具有用于向应用软件提供时间戳的内部时钟。 处理器轮流作为同步主机。 本主机向另一个（“从”）处理器发送“请求”时间戳（指示根据本地时钟发送的时间）。 每个从属处理器通过根据接收到的请求时间戳返回一个“响应”时间戳（指示根据本地从属时钟发送响应的时间）。 主人从接收到响应时间和包含的时间戳计算时钟调整值。 这允许异步时钟被同步，以便可以在处理器之间有效地比较应用程序时间戳。

    Technique to virtualize processor input/output resources
    8.
    发明授权
    Technique to virtualize processor input/output resources 有权
    虚拟化处理器输入/输出资源的技术

    公开(公告)号：US07849327B2

    公开(公告)日：2010-12-07

    申请号：US11040261

    申请日：2005-01-19

    申请人： Hin L. Leung ,  Kushagra V. Vaid ,  Amy L. Santoni ,  Dale Morris ,  Jonathan Ross

    发明人： Hin L. Leung ,  Kushagra V. Vaid ,  Amy L. Santoni ,  Dale Morris ,  Jonathan Ross

    IPC分类号： G06F11/30 ,  G06F12/14

    CPC分类号： G06F9/4812 ,  G06F9/45558 ,  G06F2009/45579

    摘要： A technique to improve the performance of virtualized input/output (I/O) resources of a microprocessor within a virtual machine environment. More specifically, embodiments of the invention enable accesses of virtualized I/O resources to be made by guest software without necessarily invoking host software. Furthermore, embodiments of the invention enable more efficient delivery of interrupts to guest software by alleviating the need for host software to be invoked in the delivery process.

    摘要翻译： 一种提高虚拟机环境中微处理器的虚拟化输入/输出（I / O）资源的性能的技术。 更具体地，本发明的实施例使得能够由客户软件访问虚拟化I / O资源，而不必调用主机软件。 此外，本发明的实施例通过减轻在传送过程中调用主机软件的需要，可以更有效地将中断传送给客户软件。

    Technique to virtualize processor input/output resources
    9.
    发明申请
    Technique to virtualize processor input/output resources 有权
    虚拟化处理器输入/输出资源的技术

    公开(公告)号：US20060236094A1

    公开(公告)日：2006-10-19

    申请号：US11040261

    申请日：2005-01-19

    申请人： Hin Leung ,  Kushagra Vaid ,  Amy Santoni ,  Dale Morris ,  Jonathan Ross

    发明人： Hin Leung ,  Kushagra Vaid ,  Amy Santoni ,  Dale Morris ,  Jonathan Ross

    IPC分类号： H04L9/00

    CPC分类号： G06F9/4812 ,  G06F9/45558 ,  G06F2009/45579

    摘要： A technique to improve the performance of virtualized input/output (I/O) resources of a microprocessor within a virtual machine environment. More specifically, embodiments of the invention enable accesses of virtualized I/O resources to be made by guest software without necessarily invoking host software. Furthermore, embodiments of the invention enable more efficient delivery of interrupts to guest software by alleviating the need for host software to be invoked in the delivery process.

    摘要翻译： 一种提高虚拟机环境中微处理器的虚拟化输入/输出（I / O）资源的性能的技术。 更具体地，本发明的实施例使得能够由客户软件访问虚拟化I / O资源，而不必调用主机软件。 此外，本发明的实施例通过减轻在传送过程中调用主机软件的需要，可以更有效地将中断传送给客户软件。