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公开(公告)号：US08210744B2
公开(公告)日：2012-07-03
申请号：US12645727
申请日：2009-12-23
Applicant: Yoon-Jae Shin , Sang-Jin Byun
Inventor： Yoon-Jae Shin , Sang-Jin Byun
Abstract: An apparatus for detecting a temperature using transistors includes a plurality of temperature detecting units that become selectively active according to predetermined temperature intervals; and a detection signal output unit that generates detection signals according to the signals transmitted by the plurality of temperature detecting units, and outputs the detection signals.
Abstract translation: 使用晶体管检测温度的装置包括多个温度检测单元，其根据预定的温度间隔变得有选择地活动; 以及检测信号输出单元，其根据由多个温度检测单元发送的信号产生检测信号，并输出检测信号。
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公开(公告)号：US07994851B2
公开(公告)日：2011-08-09
申请号：US12511323
申请日：2009-07-29
Applicant: Sang Jin Byun , Jae Hoon Shim , Hyun Kyu Yu
Inventor： Sang Jin Byun , Jae Hoon Shim , Hyun Kyu Yu
CPC classification number: H04L27/233 , H04L27/2338
Abstract: A PSK demodulator using a time-to-digital converter includes: a filter unit that performs band pass filtering on a PSK signal; an amplitude limiting unit that limits the amplitude of an output signal of the filter unit; a clock signal generating unit that generates a clock signal; and a time-to-digital converter that samples the phase of an output signal of the amplitude limiting unit according to the clock signal and outputs a digital signal having a value corresponding to the phase of the PSK signal. Power consumption can be reduced and a circuit implementation can be simplified.
Abstract translation: 使用时间 - 数字转换器的PSK解调器包括：对PSK信号执行带通滤波的滤波器单元; 幅度限制单元，限制滤波器单元的输出信号的幅度; 时钟信号生成单元，生成时钟信号; 以及时间 - 数字转换器，其根据时钟信号对幅度限制单元的输出信号的相位进行采样，并输出具有与PSK信号的相位对应的值的数字信号。 可以降低功耗并简化电路实现。
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公开(公告)号：US20100098133A1
公开(公告)日：2010-04-22
申请号：US12645727
申请日：2009-12-23
Applicant: Yoon-Jae Shin , Sang-Jin Byun
Inventor： Yoon-Jae Shin , Sang-Jin Byun
IPC: G01K7/00
Abstract: An apparatus for detecting a temperature using transistors includes a plurality of temperature detecting units that become selectively active according to predetermined temperature intervals; and a detection signal output unit that generates detection signals according to the signals transmitted by the plurality of temperature detecting units, and outputs the detection signals.
Abstract translation: 使用晶体管检测温度的装置包括多个温度检测单元，其根据预定的温度间隔变得有选择地活动; 以及检测信号输出单元，其根据由多个温度检测单元发送的信号产生检测信号，并输出检测信号。
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公开(公告)号：US07643598B2
公开(公告)日：2010-01-05
申请号：US11204957
申请日：2005-08-16
Applicant: Sang-Jin Byun , Hyun-Kyu Yu
Inventor： Sang-Jin Byun , Hyun-Kyu Yu
IPC: H04L7/00
CPC classification number: G01R23/10 , G01R23/005
Abstract: Provided is a frequency lock detector which includes one counter and a clock number difference detector for detecting a clock number difference while not increasing complexity according to the counting number N to compare the frequencies of two clock signals whose phases are not synchronous to each other and determine whether the difference between the frequencies of the two signals is within a desired frequency accuracy. The frequency lock detector includes: a counter for counting the number of clocks of a reference clock signal inputted from outside; a clock number difference detector for detecting a difference between the clock number of the reference clock signal and the clock number of a recovered clock signal whose phase is not synchronous to the phase of the reference clock signal; and a lock determiner for determining a frequency lock based on result values of the counter and the clock number difference detector.
Abstract translation: 提供一种频率锁定检测器，其包括一个计数器和时钟数差分检测器，用于检测时钟数差，同时根据计数数N不增加复杂度，以比较相位彼此不同步的两个时钟信号的频率，并确定 两个信号的频率之间的差异是否在期望的频率精度内。 频率锁定检测器包括：用于对从外部输入的参考时钟信号的时钟数进行计数的计数器; 时钟数差检测器，用于检测参考时钟信号的时钟数与其相位与参考时钟信号的相位不同步的恢复时钟信号的时钟数之间的差; 以及锁定确定器，用于基于计数器和时钟数差分检测器的结果值来确定频率锁定。
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公开(公告)号：US07436266B2
公开(公告)日：2008-10-14
申请号：US11644506
申请日：2006-12-22
Applicant: Sang-Jin Byun , Cheon-Soo Kim
Inventor： Sang-Jin Byun , Cheon-Soo Kim
IPC: H03B5/12
Abstract: Provided is an Inductor-Capacitor (LC) quadrature Voltage Controlled Oscillator (VCO) having a startup circuit which can accurately select one of +90° and −90° as a phase difference between two clocks generated by the LC quadrature VCO by embodying the startup circuit therein by using a phase detector and a controller. The LC quadrature VCO includes a first LC tank for generating a second clock signal and a fourth clock signal, a second LC tank for generating a first clock signal and a third clock signal, a phase detector for receiving the clock signals from the first LC tank and the second LC tank, and detecting whether a phase difference between the clocks is +90° or −90°, and a controller for discriminating whether phase information detected by the phase detector is equivalent to a phase difference between clocks required by the external signal processing unit, and changing an operation mode of the first LC tank and/or the second LC tank on the basis of the discrimination result of the phase difference between the clocks.
Abstract translation: 提供了一种具有启动电路的电感电容器（LC）正交压控振荡器（VCO），该启动电路可以通过体现启动而精确地选择+ 90°和-90°之一作为由LC正交VCO产生的两个时钟之间的相位差 电路中使用相位检测器和控制器。 LC正交VCO包括用于产生第二时钟信号的第一LC箱和第四时钟信号，用于产生第一时钟信号和第三时钟信号的第二LC箱，用于从第一LC箱接收时钟信号的相位检测器 和第二LC箱，并且检测时钟之间的相位差是否为+ 90°或-90°;以及控制器，用于鉴别由相位检测器检测的相位信息是否等于外部信号所需的时钟之间的相位差 处理单元，并且基于时钟之间的相位差的判别结果来改变第一LC箱和/或第二LC箱的操作模式。
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Patent Agency Ranking
16.发明申请公开(公告)号：US20070134852A1
公开(公告)日：2007-06-14
申请号：US11523212
申请日：2006-09-19
Applicant: Sang Jin Byun , Hyun Kyu Yu
Inventor： Sang Jin Byun , Hyun Kyu Yu
IPC: H01L21/82
CPC classification number: H01L27/0207
Abstract: Provided are a layout method of a power line for a semiconductor integrated circuit and a semiconductor integrated circuit manufactured by the layout method. The layout method includes the steps of: forming a decoupling capacitor on a substrate; laying out a first metal layer, connected to the decoupling capacitor through a contact, above a region where the decoupling capacitor is formed so as to cover the decoupling capacitor; and laying out a second metal layer above a region where the first metal layer is formed. Therefore, the metal layers and the decoupling capacitor are laid out in the same region so that a chip area can be prevented from being additionally consumed at the time of laying out the decoupling capacitor, and degradation which may occur due to connection line resistance from the power lines to the decoupling capacitors can be prevented.
Abstract translation: 提供了一种用于半导体集成电路的电力线的布局方法和通过布局方法制造的半导体集成电路。 布局方法包括以下步骤：在衬底上形成去耦电容器; 在形成去耦电容器的区域上方布置第一金属层，其通过接触件连接到去耦电容器，以覆盖去耦电容器; 并在其上形成第一金属层的区域上方布置第二金属层。 因此，金属层和去耦电容器布置在相同的区域中，使得在布置去耦电容器时可以防止芯片面积额外消耗，并且可能由于连接线电阻而导致的劣化 可以防止到去耦电容器的电源线。
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公开(公告)号：US06844761B2
公开(公告)日：2005-01-18
申请号：US10437417
申请日：2003-05-12
Applicant: Sang Jin Byun , Beomsup Kim , Chan-Hong Park
Inventor： Sang Jin Byun , Beomsup Kim , Chan-Hong Park
CPC classification number: H03L7/0812 , H03L7/0891 , H03L2207/14
Abstract: A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.
Abstract translation: 公开了一种系统和方法，用于为DLL提供假锁定保护器以避免假锁并确保准确的锁定。 假锁定保护器在操作期间从输入参考时钟和输出时钟的信号之间的初始延迟时间超过锁定范围时操作。 具有假锁定保护器的DLL包括参考时钟，由串联连接的多个延迟单元组成的延迟线，用于比较来自参考和输出时钟的信号的相位的相位检测器，比较器，用于控制延迟的延迟的控制器 延迟线。
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公开(公告)号：US08184496B2
公开(公告)日：2012-05-22
申请号：US12648317
申请日：2009-12-29
Applicant: Jin-Youp Cha , Sang-Jin Byun
Inventor： Jin-Youp Cha , Sang-Jin Byun
IPC: G11C17/16
CPC classification number: G11C29/785 , G11C17/16
Abstract: A semiconductor device includes a sensing unit configured to sense whether a value of a programming sensing node is within a predefined range, a fuse connected to the programming sensing node, a programming voltage supplying unit configured to supply a programming voltage to the programming sensing node, and a transferring unit configured to transfer the value of the programming sensing node in response to the sensing result of the sensing unit.
Abstract translation: 半导体器件包括感测单元，其被配置为感测编程感测节点的值是否在预定范围内，连接到编程感测节点的熔丝，编程电压提供单元，其被配置为向编程感测节点提供编程电压， 以及传送单元，其被配置为响应于感测单元的感测结果传送编程感测节点的值。
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公开(公告)号：US07661879B2
公开(公告)日：2010-02-16
申请号：US11584651
申请日：2006-10-23
Applicant: Yoon-Jae Shin , Sang-Jin Byun
Inventor： Yoon-Jae Shin , Sang-Jin Byun
IPC: G01K7/01
Abstract: An apparatus for detecting a temperature using transistors includes a plurality of temperature detecting units that become selectively active according to predetermined temperature intervals; and a detection signal output unit that generates detection signals according to the signals transmitted by the plurality of temperature detecting units, and outputs the detection signals.
Abstract translation: 使用晶体管检测温度的装置包括多个温度检测单元，其根据预定的温度间隔变得有选择地活动; 以及检测信号输出单元，其根据由多个温度检测单元发送的信号产生检测信号，并输出检测信号。
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20.发明授权公开(公告)号：US07456063B2
公开(公告)日：2008-11-25
申请号：US11523212
申请日：2006-09-19
Applicant: Sang Jin Byun , Hyun Kyu Yu
Inventor： Sang Jin Byun , Hyun Kyu Yu
IPC: H01L21/8242
CPC classification number: H01L27/0207
Abstract: Provided are a layout method of a power line for a semiconductor integrated circuit and a semiconductor integrated circuit manufactured by the layout method. The layout method includes the steps of: forming a decoupling capacitor on a substrate; laying out a first metal layer, connected to the decoupling capacitor through a contact, above a region where the decoupling capacitor is formed so as to cover the decoupling capacitor; and laying out a second metal layer above a region where the first metal layer is formed. Therefore, the metal layers and the decoupling capacitor are laid out in the same region so that a chip area can be prevented from being additionally consumed at the time of laying out the decoupling capacitor, and degradation which may occur due to connection line resistance from the power lines to the decoupling capacitors can be prevented.
Abstract translation: 提供了一种用于半导体集成电路的电力线的布局方法和通过布局方法制造的半导体集成电路。 布局方法包括以下步骤：在衬底上形成去耦电容器; 在形成去耦电容器的区域上方布置第一金属层，其通过接触件连接到去耦电容器，以覆盖去耦电容器; 并在其上形成第一金属层的区域上方布置第二金属层。 因此，金属层和去耦电容器布置在相同的区域中，使得在布置去耦电容器时可以防止芯片面积额外消耗，并且可能由于连接线电阻而导致的劣化 可以防止到去耦电容器的电源线。
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