公开(公告)号：US07675451B2

公开(公告)日：2010-03-09

申请号：US12232636

申请日：2008-09-22

Applicant: Shigemitsu Murayama ,  Yasuhide Shimizu ,  Kohei Kudo ,  Hiroaki Yatsuda

Inventor： Shigemitsu Murayama ,  Yasuhide Shimizu ,  Kohei Kudo ,  Hiroaki Yatsuda

IPC: H03M1/36

CPC classification number: H03M1/146 ,  H03M1/1215 ,  H03M1/365

Abstract: A serial-parallel type analog-to-digital converter includes a reference voltage generator, a higher bit comparing portion and a lower bit comparing portion, and a reference voltage selecting portion, wherein the lower bit comparing portion includes the plurality of comparison stages.

Abstract translation: 串行并行型模数转换器包括参考电压发生器，较高位比较部分和低位比较部分以及参考电压选择部分，其中低位比较部分包括多个比较级。

公开(公告)号：US07564395B2

公开(公告)日：2009-07-21

申请号：US11936428

申请日：2007-11-07

Applicant: Shigemitsu Murayama ,  Kohei Kudo ,  Yasuhide Shimizu

Inventor： Shigemitsu Murayama ,  Kohei Kudo ,  Yasuhide Shimizu

IPC: H03M1/12

CPC classification number: H03M1/365

Abstract: A subranging analog-to-digital converter is disclosed. The converter includes: a divided voltage generation circuit that equally divides a range of a predetermined voltage, and generates 2m+1 divided voltages; a higher-order conversion circuit that generates a signal for higher-order m bits of the digital signal by comparing the analog signal with the 2m−1 or less of the 2m+1 divided voltages; a switch circuit that selects at least two of the 2m+1 divided voltages based on information provided by the higher-order conversion circuit; a lower-order conversion circuit that generates a signal for lower-order n bits (n=N−m) of the digital signal by comparing the analog signal with the divided voltages being a selection result of the switch circuit; and an encoder that generates the digital signal based on the signal provided by the higher-order conversion circuit and the signal provided by the lower-order conversion circuit.

Abstract translation: 公开了一种子范围模数转换器。 转换器包括：分压电压产生电路，其等分预定电压的范围，并产生2m + 1分压; 通过将模拟信号与2m + 1分压的2m-1或更小来比较，生成数字信号的高位m位的信号的高阶转换电路; 开关电路，其基于由所述高阶转换电路提供的信息选择所述2m + 1分压中的至少两个电压; 通过将模拟信号与作为开关电路的选择结果的分压电路进行比较来生成数字信号的低阶n位（n = N-m）的信号的低阶转换电路; 以及基于由高阶转换电路提供的信号和由低阶转换电路提供的信号产生数字信号的编码器。

公开(公告)号：US20080180296A1

公开(公告)日：2008-07-31

申请号：US11936428

申请日：2007-11-07

Applicant: Shigemitsu Murayama ,  Kohei Kudo ,  Yasuhide Shimizu

Inventor： Shigemitsu Murayama ,  Kohei Kudo ,  Yasuhide Shimizu

IPC: H03M1/12

CPC classification number: H03M1/365

Abstract: A subranging analog-to-digital converter is disclosed. The converter includes: a divided voltage generation circuit that equally divides a range of a predetermined voltage, and generates 2m+1 divided voltages; a higher-order conversion circuit that generates a signal for higher-order m bits of the digital signal by comparing the analog signal with the 2m−1 or less of the 2m+1 divided voltages; a switch circuit that selects at least two of the 2m+1 divided voltages based on information provided by the higher-order conversion circuit; a lower-order conversion circuit that generates a signal for lower-order n bits (n=N−m) of the digital signal by comparing the analog signal with the divided voltages being a selection result of the switch circuit; and an encoder that generates the digital signal based on the signal provided by the higher-order conversion circuit and the signal provided by the lower-order conversion circuit.

Abstract translation: 公开了一种子范围模数转换器。 转换器包括：分压电压产生电路，其等分预定电压的范围，并产生2×1 + 1分压; 一个高阶转换电路，通过将模拟信号与2μs/ 2以上的2×2以下的比较生成用于数字信号的高位m位的信号 > +1分压; 开关电路，其基于由所述高阶转换电路提供的信息选择所述2 + 1分频电压中的至少两个; 通过将模拟信号与作为开关电路的选择结果的分压电路进行比较来生成数字信号的低阶n位（n = N-m）的信号的低阶转换电路; 以及基于由高阶转换电路提供的信号和由低阶转换电路提供的信号产生数字信号的编码器。

公开(公告)号：US20090102693A1

公开(公告)日：2009-04-23

申请号：US12232636

申请日：2008-09-22

Applicant: Shigemitsu Murayama ,  Yasuhide Shimizu ,  Kohei Kudo ,  Hiroaki Yatsuda

Inventor： Shigemitsu Murayama ,  Yasuhide Shimizu ,  Kohei Kudo ,  Hiroaki Yatsuda

IPC: H03M1/34

CPC classification number: H03M1/146 ,  H03M1/1215 ,  H03M1/365

Abstract: A serial-parallel type analog-to-digital converter includes a reference voltage generator, a higher bit comparing portion and a lower bit comparing portion, and a reference voltage selecting portion, wherein the lower bit comparing portion includes the plurality of comparison stages.

Abstract translation: 串行并行型模数转换器包括参考电压发生器，较高位比较部分和低位比较部分以及参考电压选择部分，其中低位比较部分包括多个比较级。

公开(公告)号：US20070152722A1

公开(公告)日：2007-07-05

申请号：US11624270

申请日：2007-01-18

Applicant: Yasuhide Shimizu ,  Shigemitsu Murayama ,  Yukitoshi Yamashita ,  Junji Toyomura

Inventor： Yasuhide Shimizu ,  Shigemitsu Murayama ,  Yukitoshi Yamashita ,  Junji Toyomura

IPC: H03L7/06

CPC classification number: G11C27/024 ,  G11C27/026 ,  H03F3/45089 ,  H03F2203/45626 ,  H03F2203/45631 ,  H03F2203/45651 ,  H03F2203/45696 ,  H03F2203/45702 ,  H03F2203/45726 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/142 ,  H03M1/206 ,  H03M1/365

Abstract: A comparator includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor and which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains maintaining a voltage at the output end of the sampling capacitor to be constant. The input signal is compared with the reference signal.

Abstract translation: 比较器包括采样电容器，第一开关单元，其连接到采样电容器的输入端并将输入信号施加到采样电容器的输入端;第二开关单元，连接到采样电容器的输入端; 采样电容器，并且将采样电容器的输入端施加参考信号，以源极跟随器连接方式或射极跟随器连接方式连接到采样电容器的输出端的输出晶体管，以及连接到所述采样电容器的第三开关单元 到采样电容器的输出端，并且维持采样电容器输出端的电压保持恒定。 将输入信号与参考信号进行比较。

公开(公告)号：US07215159B2

公开(公告)日：2007-05-08

申请号：US10818776

申请日：2004-04-06

Applicant: Yasuhide Shimizu ,  Shigemitsu Murayama ,  Yukitoshi Yamashita ,  Junji Toyomura

Inventor： Yasuhide Shimizu ,  Shigemitsu Murayama ,  Yukitoshi Yamashita ,  Junji Toyomura

IPC: H03K5/22 ,  G11C27/02

CPC classification number: G11C27/024 ,  G11C27/026 ,  H03F3/45089 ,  H03F2203/45626 ,  H03F2203/45631 ,  H03F2203/45651 ,  H03F2203/45696 ,  H03F2203/45702 ,  H03F2203/45726 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/142 ,  H03M1/206 ,  H03M1/365

Abstract: A comparator includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor and which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains maintaining a voltage at the output end of the sampling capacitor to be constant. The input signal is compared with the reference signal.

Abstract translation: 比较器包括采样电容器，第一开关单元，其连接到采样电容器的输入端并将输入信号施加到采样电容器的输入端;第二开关单元，连接到采样电容器的输入端; 采样电容器，并且将采样电容器的输入端施加参考信号，以源极跟随器连接方式或射极跟随器连接方式连接到采样电容器的输出端的输出晶体管，以及连接到所述采样电容器的第三开关单元 到采样电容器的输出端，并且维持采样电容器输出端的电压保持恒定。 将输入信号与参考信号进行比较。

公开(公告)号：US20070085653A1

公开(公告)日：2007-04-19

申请号：US11544610

申请日：2006-10-10

Applicant: Yasuhide Shimizu ,  Shigemitsu Murayama ,  Kohei Kudo ,  Hiroaki Yatsuda

Inventor： Yasuhide Shimizu ,  Shigemitsu Murayama ,  Kohei Kudo ,  Hiroaki Yatsuda

IPC: H01C10/16

CPC classification number: H01L27/0802 ,  H01L28/20

Abstract: A semiconductor device includes a semiconductor substrate and a ladder resistor formed on the semiconductor substrate. The ladder resistor includes a plurality of elongated resistor portions arranged in parallel with each other, a plurality of connection portions that connect the resistor portions at predetermined intervals in a longitudinal direction of the resistor portions, and a plurality of voltage extraction portions provided in order to extract voltages at the individual connection portions.

Abstract translation: 半导体器件包括形成在半导体衬底上的半导体衬底和梯形电阻。 梯形电阻器包括彼此平行布置的多个细长的电阻器部分，多个连接部分，其在电阻器部分的纵向方向上以预定间隔连接电阻器部分，以及多个电压提取部分， 在各个连接部分提取电压。