公开(公告)号：US5099240A

公开(公告)日：1992-03-24

申请号：US583632

申请日：1990-09-17

Applicant: Yuuichi Nakatani ,  Hironori Miyake

Inventor： Yuuichi Nakatani ,  Hironori Miyake

IPC: H03M1/14 ,  H03M1/06 ,  H03M1/12 ,  H03M1/36

CPC classification number: H03M1/069 ,  H03M1/1215 ,  H03M1/142 ,  H03M1/144 ,  H03M1/146

Abstract: A multiple-clock-cycle subranging type A/D converter utilizing sufficient fine steps in the LSB identification to cover two complete coarse steps so that there are no gaps in the fine steps and no potential errors. Also, two LSB encoders can be utilized, one during each clock cycle, to increase the speed of the A/D converter. The components of the A/D converter are positioned on a semiconductor chip so that noise from electronic switches is not introduced into the reference voltage ladder.

公开(公告)号：US3149308A

公开(公告)日：1964-09-15

申请号：US85176659

申请日：1959-11-09

Applicant: SPACE GENERAL CORP

Inventor： LEHAN FRANK W ,  NEWBERRY ALVIN W ,  SANDERS RAY W

IPC: H03M1/00 ,  H04L17/30

CPC classification number: H04L17/30 ,  H03M1/142

公开(公告)号：US2870406A

公开(公告)日：1959-01-20

申请号：US66331657

申请日：1957-06-03

Applicant: SMITH CALDWELL P

Inventor： SMITH CALDWELL P

IPC: G01R19/10 ,  G01R19/17 ,  G01R19/18 ,  G10L19/02 ,  H03M1/00

CPC classification number: G10L19/02 ,  G01R19/10 ,  G01R19/17 ,  G01R19/18 ,  H03M1/142 ,  H03M1/504

公开(公告)号：US09344101B2

公开(公告)日：2016-05-17

申请号：US14830623

申请日：2015-08-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi Ueki

IPC: H03M1/12 ,  H03M1/00

CPC classification number: H03M1/002 ,  H03M1/12 ,  H03M1/142

Abstract: In order to reduce power consumption, a semiconductor device includes an RTC for generating a piece of time information and a first activation signal SW3, a comparator for determining whether the value of an analog input signal exists within a predetermined range, an AD conversion circuit for converting the analog input signal to a digital signal in response to a common activation signal, and a CPU for processing the digital signal in response to the common activation signal. When the analog input signal does not exist within the predetermined rang, the comparator generates the common activation signal. Then, the CPU stores the piece of digital information corresponding to the digital signal as well as the piece of time information from the RTC into a storage circuit.

Abstract translation: 为了降低功耗，半导体器件包括用于产生一段时间信息的RTC和第一激活信号SW3，用于确定模拟输入信号的值是否存在于预定范围内的比较器，用于 响应于公共激活信号将模拟输入信号转换为数字信号，以及CPU，用于响应于公共激活信号来处理数字信号。 当模拟输入信号不在预定范围内时，比较器产生公共激活信号。 然后，CPU将与数字信号相对应的数字信息以及来自RTC的时间信息存储到存储电路中。

公开(公告)号：US08120388B2

公开(公告)日：2012-02-21

申请号：US11624270

申请日：2007-01-18

Applicant: Yasuhide Shimizu ,  Shigemitsu Murayama ,  Yukitoshi Yamashita ,  Junji Toyomura

Inventor： Yasuhide Shimizu ,  Shigemitsu Murayama ,  Yukitoshi Yamashita ,  Junji Toyomura

IPC: H03K5/22 ,  G11C27/02

CPC classification number: G11C27/024 ,  G11C27/026 ,  H03F3/45089 ,  H03F2203/45626 ,  H03F2203/45631 ,  H03F2203/45651 ,  H03F2203/45696 ,  H03F2203/45702 ,  H03F2203/45726 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/142 ,  H03M1/206 ,  H03M1/365

Abstract: A comparator includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor and which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains maintaining a voltage at the output end of the sampling capacitor to be constant. The input signal is compared with the reference signal.

Abstract translation: 比较器包括采样电容器，第一开关单元，其连接到采样电容器的输入端并将输入信号施加到采样电容器的输入端;第二开关单元，连接到采样电容器的输入端; 采样电容器，并且将采样电容器的输入端施加参考信号，以源极跟随器连接方式或射极跟随器连接方式连接到采样电容器的输出端的输出晶体管，以及连接到采样电容器的第三开关单元 到采样电容器的输出端，并且维持采样电容器输出端的电压保持恒定。 将输入信号与参考信号进行比较。

公开(公告)号：US20040263376A1

公开(公告)日：2004-12-30

申请号：US10818776

申请日：2004-04-06

Applicant: Sony Corporation

Inventor： Yasuhide Shimizu ,  Shigemitsu Murayama ,  Yukitoshi Yamashita ,  Junji Toyomura

IPC: H03M001/12

CPC classification number: G11C27/024 ,  G11C27/026 ,  H03F3/45089 ,  H03F2203/45626 ,  H03F2203/45631 ,  H03F2203/45651 ,  H03F2203/45696 ,  H03F2203/45702 ,  H03F2203/45726 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/142 ,  H03M1/206 ,  H03M1/365

Abstract: A comparator includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor and which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains maintaining a voltage at the output end of the sampling capacitor to be constant. The input signal is compared with the reference signal.

公开(公告)号：US20010040523A1

公开(公告)日：2001-11-15

申请号：US09842061

申请日：2001-04-26

Applicant: Sony Corporation.

Inventor： Yuji Gendai

IPC: H03M001/36

CPC classification number: H03M1/142 ,  H03M1/14 ,  H03M1/365

Abstract: An ADC having a sparkle suppression capability equivalent to that of a full bit Gray encoding method and preventing criss-crossing of interconnections nor an increase of the pipeline delay, wherein a resistor string for generating reference voltages to be compared with an analog input signal is folded 2n times or a multiple thereof corresponding to the number n of most significant bits of the output bit ADB of the related ADC. It has a first encoder for encoding the most significant n bits and outputting a Gray code, second encoders for encoding least significant bits and outputting the same, a first output circuit for converting the Gray code output from the first encoder to a binary code and generating most significant n bits, and a second output circuit for generating least significant bits by using the digital code generated by the first output circuit and the output of the second encoder.

Abstract translation: 具有与完全灰度编码方法相同的闪光抑制能力并防止互连交叉的ADC的ADC或者管线延迟的增加，其中用于产生与模拟输入信号进行比较的参考电压的电阻串被折叠 2n倍或其相应于相关ADC的输出位ADB的最高有效位数n的倍数。 它具有用于对最高有效n位进行编码并输出格雷码的第一编码器，用于编码最低有效位并输出的第二编码器，用于将从第一编码器输出的格雷码转换为二进制码的第一输出电路， 最高有效n位，以及第二输出电路，用于通过使用由第一输出电路产生的数字代码和第二编码器的输出来产生最低有效位。

公开(公告)号：US20230252276A1

公开(公告)日：2023-08-10

申请号：US17727650

申请日：2022-04-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G06N3/063 ,  G06F17/12 ,  H03M1/14

CPC classification number: G06N3/0635 ,  G06F17/12 ,  H03M1/142

Abstract: Numerous examples are disclosed for performing calibration of various electrical parameters in a deep learning artificial neural network. In one example, a system comprises a digital-to-analog converter for receiving an input of k bits and generating a first analog output, a mapping scalar for converting the first analog output into a second analog output, and an analog-to-digital converter for generating an output of n bits from the second analog output, where n is a different value than k.

公开(公告)号：US20180069565A1

公开(公告)日：2018-03-08

申请号：US15697216

申请日：2017-09-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Norio SUGITA

IPC: H03M1/34 ,  H03M1/18 ,  H03M1/12 ,  H03M1/14

CPC classification number: H03M1/34 ,  H03M1/0621 ,  H03M1/123 ,  H03M1/142 ,  H03M1/148 ,  H03M1/182

Abstract: A semiconductor device includes an AD conversion unit that performs AD conversion on an input signal based on a reference voltage to be supplied, a reference voltage detection unit that detects the reference voltage supplied to the AD conversion unit, and a control unit that corrects a result of the AD conversion by the AD conversion unit in accordance with the reference voltage detected by the reference voltage detection unit. Thereby, AD conversion can be performed accurately even when a reference voltage varies.

公开(公告)号：US20070152722A1

公开(公告)日：2007-07-05

申请号：US11624270

申请日：2007-01-18

Applicant: Yasuhide Shimizu ,  Shigemitsu Murayama ,  Yukitoshi Yamashita ,  Junji Toyomura

Inventor： Yasuhide Shimizu ,  Shigemitsu Murayama ,  Yukitoshi Yamashita ,  Junji Toyomura

IPC: H03L7/06

CPC classification number: G11C27/024 ,  G11C27/026 ,  H03F3/45089 ,  H03F2203/45626 ,  H03F2203/45631 ,  H03F2203/45651 ,  H03F2203/45696 ,  H03F2203/45702 ,  H03F2203/45726 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/142 ,  H03M1/206 ,  H03M1/365

Abstract: A comparator includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor and which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains maintaining a voltage at the output end of the sampling capacitor to be constant. The input signal is compared with the reference signal.

Abstract translation: 比较器包括采样电容器，第一开关单元，其连接到采样电容器的输入端并将输入信号施加到采样电容器的输入端;第二开关单元，连接到采样电容器的输入端; 采样电容器，并且将采样电容器的输入端施加参考信号，以源极跟随器连接方式或射极跟随器连接方式连接到采样电容器的输出端的输出晶体管，以及连接到所述采样电容器的第三开关单元 到采样电容器的输出端，并且维持采样电容器输出端的电压保持恒定。 将输入信号与参考信号进行比较。