Abstract:
A display apparatus comprises a display panel, a gate driving circuit, and a pulse generation circuit. The display panel displays an image. The gate driving circuit drives the display panel according to a pulse signal generated by the pulse generation circuit. The pulse generation circuit comprises a histogram analysis element and a gate pulse modulator. The histogram analysis element calculates a gray level ratio of the image, and compares the gray level ratio with at least one threshold value to generate at least one control signal. The operative time of the pulse signal is determined in response to the control signal.
Abstract:
A thin film transistor (TFT) array substrate including a substrate, scan lines and data lines both disposed on the substrate, and pixel structures is provided. A plurality of pixel areas is defined by the scan lines and the data lines on the substrate. Each scan line has a driving signal input terminal and an end terminal. Each pixel area includes a first sub-pixel area and a second sub-pixel area. The pixel structures are respectively disposed in the pixel areas and driven by the scan lines and the data lines. Each pixel structure in the respective pixel area includes a first TFT corresponding to the first sub-pixel area and a second TFT corresponding to the second sub-pixel area. Besides, ratios of a channel width to a channel length of the second TFTs connected to the same scan line increase gradually from the driving signal input terminal to the end terminal.
Abstract:
A pixel electrode structure of a transflective liquid crystal display comprises a reflective electrode laid on a surface of the gate-insulating layer, a dielectric layer covering the reflective electrode, and a transmissive electrode on the dielectric layer and connected to the reflective electrode.
Abstract:
A liquid crystal display includes a gate driver, a data driver and a pixel matrix. The gate driver is for outputting a plurality of gate signals successively. The data driver is for providing a plurality of data signals. The pixel matrix includes a number of pixels. Each pixel includes a first sub-pixel, a second sub-pixel and a voltage coupling device. The voltage coupling device is coupled between the first sub-pixel and the second sub-pixel such that pixel voltages of the first sub-pixel and the second sub-pixel are different and have relevant variation.
Abstract:
A liquid crystal display includes a light source for emitting light, a first substrate, a second substrate parallel to and facing the first substrate, and a plurality of pixel units formed between the first substrate and the second substrate. At least one pixel unit comprises a reflecting element disposed on the first substrate for reflecting light from the light source, and a photo-sensing element, formed on the second substrate, for outputting a sensing parameter based on light reflected from the reflecting member. Each reflecting element is extended out of the first substrate and faces to one of the plurality of photo-sensing elements. A position of the force applied on the first substrate is determined by detecting a variation of the sensing parameter outputted by the photo-sensing element.
Abstract:
A PSA LCD panel includes a plurality of pixel units. Each of the pixel units includes a first pixel electrode and a second pixel electrode separated from the first pixel electrode. Each of the first and second pixel electrodes has a pattern scattered from a center in such a manner to form four domains.
Abstract:
A multi-domain vertical alignment (MVA) liquid crystal display panel includes an array substrate, a color filter (CF) substrate arranged in parallel to the array substrate, a plurality of bump patterns disposed on the CF substrate, and a plurality of transparent electrode patterns disposed on the array substrate. Each bump pattern includes a main bump corresponding to a pixel region, and at least one bump wing corresponding to a scan line or a data line. Each main bump includes a first protrusion connected to a side of the main bump. Each transparent electrode pattern includes a main slit. The transparent electrode pattern further includes a plurality of fine slits disposed in an inner side and in an outer side of the main slit. The fine slits disposed in the outer side of the main slit near the data line have different lengths.
Abstract:
A liquid crystal display is provided. An array structure of active device includes a substrate, a plurality of gate lines, a plurality of data lines, a plurality of active devices and a plurality of pixel electrodes thereon. Each of the pixel electrodes has several fine slits, and there is an angle included by the direction of electric field that crosses over the fine slit and the rubbing direction of liquid crystal layer. When applying voltage on the pixel electrodes, the liquid crystal molecules are to be twisted and transited from splay state into bend state rapidly. After that, the spreading elastic force between liquid crystal molecules could shorten the time of transition of the liquid crystal molecules in all pixel regions. Therefore, the optically self-compensated birefringence liquid crystal display can be warmed up faster.
Abstract:
A liquid crystal display panel includes a first substrate, a second substrate, a first electrode, a second electrode, a third electrode, an isolating layer, and a conductor. The first electrode is disposed between the first substrate and the isolating layer, on which the conductor is disposed. Each of the second and third electrodes is disposed on the second substrate and includes a contact surface. The second and third electrodes are not in contact with each other and are separated by a gap. The conductor is disposed in accordance with the location of the gap.
Abstract:
A gate driver includes cascade-connected driving stages. Each of the driving stages includes a first shift register circuit and a second shift register circuit. The first shift register circuit is configured for outputting a present stage driving signal and a next stage driving signal. The second shift register circuit is electrically coupled to the first shift register circuit and configured for outputting a present stage gate signal, a first next stage gate signal, and a second next stage gate signal. Furthermore, a display panel is also provided herein.