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    Programmable logic device with unified cell structure including signal interface bumps
    11.
    发明授权
    Programmable logic device with unified cell structure including signal interface bumps 有权
    可编程逻辑器件具有统一的单元结构，包括信号接口凸块

    公开(公告)号：US06351144B1

    公开(公告)日：2002-02-26

    申请号：US09615926

    申请日：2000-07-13

    Applicant: Sergey Shumarayev ,  Wei-Jen Huang ,  Rakesh Patel

    Inventor： Sergey Shumarayev ,  Wei-Jen Huang ,  Rakesh Patel

    IPC: G06F738

    CPC classification number: H01L23/5382 ,  H01L27/118 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A programmable logic device including a set of aligned unified cells, with each unified cell including one or more logic array blocks and a set of signal interface bumps. An input/output band of each unified cell is aligned with input/output bands of adjacent unified cells. A trace is positioned between each signal interface bump and the input/output band. The input/output band of each unified cell is responsible for providing an input/output interface for the logic array block(s) of that unified cell. Signal interface bumps of a unified cell may be coupled to those of another cell via the package. As a result, row and column interconnect circuitry present in conventional programmable logic devices can be obviated. In another aspect of the invention, a grid of signal interface bumps is formed on a die. A package with a solder ball is positioned within the grid of signal interface bumps. A set of package routing leads is positioned between the grid of signal interface bumps and the solder ball.

    Abstract translation: 包括一组对准的统一单元的可编程逻辑器件，每个统一单元包括一个或多个逻辑阵列块和一组信号接口凸块。 每个统一单元的输入/输出带与相邻统一单元的输入/输出带对齐。 轨迹位于每个信号界面凸块和输入/输出带之间。 每个统一单元的输入/输出频带负责提供该统一单元的逻辑阵列块的输入/输出接口。 统一单元的信号接口凸起可以经由封装耦合到另一个单元的信号接口凸块。 结果，可以避免存在于常规可编程逻辑器件中的行和列互连电路。 在本发明的另一方面，在模具上形成栅格的信号界面凸块。 具有焊球的封装位于信号接口凸块的栅格内。 一组封装路由引线位于信号接口凸块和焊球之间。

    Speed negotiation for multi-speed communication devices
    14.
    发明申请
    Speed negotiation for multi-speed communication devices 有权
    多速通信设备的速度协商

    公开(公告)号：US20080317069A1

    公开(公告)日：2008-12-25

    申请号：US11821251

    申请日：2007-06-21

    Applicant: Wei-Jen Huang ,  Chih-Tsung Huang ,  Claudio DeSanti

    Inventor： Wei-Jen Huang ,  Chih-Tsung Huang ,  Claudio DeSanti

    IPC: H04J3/06

    CPC classification number: H04L5/1438

    Abstract: A method includes defining a pattern of time intervals, each time interval having a respective assigned communication speed, which alternates among multiple communication speeds supported by a first communication device. Synchronization requests are transmitted over a communication medium from the first communication device to a second communication device at the respective communication speed that is assigned in each interval in accordance with the pattern. While transmitting the synchronization requests, synchronization replies sent over the communication medium in response to the synchronization requests are received only at the respective communication speed that is assigned in each interval. Responsively to receiving the synchronization replies from the second communication device, one or more common communication speeds that are supported by both the first and the second communication devices are identified. Communication is established between the first and second communication devices over the communication medium using one of the common communication speeds.

    Abstract translation: 一种方法包括定义时间间隔的模式，每个时间间隔具有各自分配的通信速度，其在由第一通信设备支持的多个通信速度之间交替。 同步请求通过通信介质从第一通信设备以按照该模式在每个间隔中分配的相应通信速度被发送到第二通信设备。 在发送同步请求的同时，响应于同步请求通过通信介质发送的同步回复仅在每个间隔中分配的相应通信速度下被接收。 响应于从第二通信设备接收同步响应，识别由第一和第二通信设备支持的一个或多个通用通信速度。 使用公共通信速度之一，通过通信介质在第一和第二通信设备之间建立通信。

    Interconnection and input/output resources for programmable logic integrated circuit devices
    15.
    发明申请
    Interconnection and input/output resources for programmable logic integrated circuit devices 有权
    可编程逻辑集成电路器件的互连和输入/输出资源

    公开(公告)号：US20080074143A1

    公开(公告)日：2008-03-27

    申请号：US11888317

    申请日：2007-07-30

    Applicant: Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Michael Hutton ,  Victor Maruri ,  Rakesh Patel ,  Peter Kazarian ,  Andrew Leaver ,  David Mendel ,  Jim Park

    Inventor： Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Michael Hutton ,  Victor Maruri ,  Rakesh Patel ,  Peter Kazarian ,  Andrew Leaver ,  David Mendel ,  Jim Park

    IPC: H03K19/177

    CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17792

    Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

    Abstract translation: 可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。 这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。 例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。 辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

    Interconnection resources for programmable logic integrated circuit devices
    16.
    发明授权
    Interconnection resources for programmable logic integrated circuit devices 有权
    可编程逻辑集成电路器件的互连资源

    公开(公告)号：US07262635B2

    公开(公告)日：2007-08-28

    申请号：US11514692

    申请日：2006-09-01

    Applicant: James Schleicher ,  Jim Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    Inventor： James Schleicher ,  Jim Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    IPC: H03K19/177

    CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

    Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

    Abstract translation: 可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。 此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。 本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。 由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

    Interconnection and input/output resources for programmable logic integrated circuit devices
    17.
    发明申请
    Interconnection and input/output resources for programmable logic integrated circuit devices 有权
    可编程逻辑集成电路器件的互连和输入/输出资源

    公开(公告)号：US20070030029A1

    公开(公告)日：2007-02-08

    申请号：US11269867

    申请日：2005-11-07

    Applicant: Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    Inventor： Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    IPC: H03K19/177

    CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17792

    Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

    Abstract translation: 可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。 在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。 这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。 例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。 辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

    Interconnection resources for programmable logic integrated circuit devices
    18.
    发明授权
    Interconnection resources for programmable logic integrated circuit devices 有权
    可编程逻辑集成电路器件的互连资源

    公开(公告)号：US06897680B2

    公开(公告)日：2005-05-24

    申请号：US10797484

    申请日：2004-03-09

    Applicant: James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    Inventor： James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    IPC: G06F7/50 ,  G06F7/506 ,  H03K19/173 ,  H03K19/177 ,  H03K19/0177

    CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

    Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

    Abstract translation: 可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。 此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。 本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。 由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

    Driver circuitry for programmable logic devices
    19.
    发明授权
    Driver circuitry for programmable logic devices 有权
    用于可编程逻辑器件的驱动电路

    公开(公告)号：US06690195B1

    公开(公告)日：2004-02-10

    申请号：US10047810

    申请日：2002-01-15

    Applicant: Tony Ngai ,  Sergey Shumarayev ,  Wei-Jen Huang

    Inventor： Tony Ngai ,  Sergey Shumarayev ,  Wei-Jen Huang

    IPC: H03K19177

    CPC classification number: G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1778

    Abstract: Driver circuitry for programmable logic devices may include a module comprising a driver and associated hardware-programmable input and/or output routing connections. Instances of the generalized driver module may be included anywhere on the programmable logic device that driver circuitry having characteristics within the capabilities of the generalized module is needed. The circuitry of each instance of the module is hardware-customized to match the driver characteristics required for that instance. Driver circuits may be distributed throughout the interconnection conductor resources of the programmable logic device in such a way as to optimize re-buffering of signals propagating through those resources.

    Abstract translation: 用于可编程逻辑器件的驱动器电路可以包括包括驱动器和相关联的硬件可编程输入和/或输出路由连接的模块。 广义驱动器模块的实例可以包括在可编程逻辑器件的任何地方，其中需要具有广义模块能力的特性的驱动器电路。 模块的每个实例的电路都是硬件自定义的，以匹配该实例所需的驱动程序特性。 驱动器电路可以分布在可编程逻辑器件的整个互连导体资源中，以便优化通过这些资源传播的信号的重新缓冲。

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