公开(公告)号：US3965385A

公开(公告)日：1976-06-22

申请号：US531956

申请日：1974-12-12

申请人： Amos Picker ,  Wolfgang M. Feist

发明人： Amos Picker ,  Wolfgang M. Feist

IPC分类号： H01J29/44 ,  H01J31/58 ,  H01J29/45 ,  H01J31/38

CPC分类号： H01J29/44 ,  H01J31/585

摘要： A display system having a cathode ray tube signal generator in which a solid state junction target utilizes a layer of semiconductor material and a layer of dielectric material to form a junction. The signal generator may be of the monoscope type in which portions of the target are masked or it may be of the photosensitive type in which an image is projected onto the target. A signal derived from the signal generator is displayed on a second cathode ray tube.

摘要翻译： 具有阴极射线管信号发生器的显示系统，其中固态接合靶使用半导体材料层和电介质材料层以形成结。 信号发生器可以是单目镜型，其中目标的部分被掩蔽，或者它可以是将图像投影到目标上的感光类型。 从第二阴极射线管显示从信号发生器得到的信号。

公开(公告)号：US4677456A

公开(公告)日：1987-06-30

申请号：US833574

申请日：1986-02-25

申请人： Wolfgang M. Feist

发明人： Wolfgang M. Feist

IPC分类号： H01L21/762 ,  H01L29/10 ,  H01L29/737 ,  H01L27/04 ,  H01L29/06

CPC分类号： H01L29/7375 ,  H01L21/7621 ,  H01L21/76216 ,  H01L29/1004 ,  Y10S148/01 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/117 ,  Y10S148/124 ,  Y10S148/145

摘要： A semiconductor structure is provided by forming an isolation region in a portion of a semiconductor layer, forming a doped region in the semiconductor layer adjacent the isolation region, such doped region having a conductivity type opposite the conductivity type of the semiconductor layer, selectively masking a surface of the semiconductor layer exposing a portion of the doped region adjacent to the isolation region, and selectively etching the exposed portions of the adjacent doped region forming a depression having converging side walls separated from the isolation region by portions of the doped region. The semiconductor layer is an epitaxial layer providing the collector region of a transistor. The bottom portion of the depression is lightly doped to provide an active base region for the transistor. The active base region is electrically connected to the base contact through the more heavily doped region formed in the semiconductor layer. A doped polycrystalline silicon layer is formed over the bottom portion of the depression in contact with the active base region to provide an emitter contact for the transistor.

摘要翻译： 通过在半导体层的一部分中形成隔离区域形成半导体结构，在邻近隔离区域的半导体层中形成掺杂区域，该掺杂区域具有与半导体层的导电类型相反的导电类型， 所述半导体层的表面暴露出与所述隔离区相邻的所述掺杂区的一部分，并且选择性地蚀刻所述相邻掺杂区的所述暴露部分，形成具有所述掺杂区域的一部分与所述隔离区隔开的会聚侧壁的凹陷。 半导体层是提供晶体管的集电极区域的外延层。 凹陷的底部被轻掺杂以提供晶体管的有源基极区域。 有源基区通过形成在半导体层中的更高掺杂区电连接到基极接触。 掺杂多晶硅层形成在与有源基极区接触的凹陷的底部上，以提供晶体管的发射极接触。

公开(公告)号：US4569698A

公开(公告)日：1986-02-11

申请号：US739509

申请日：1985-05-31

申请人： Wolfgang M. Feist

发明人： Wolfgang M. Feist

IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L21/265 ,  H01L21/31

CPC分类号： H01L21/76216 ,  H01L21/308 ,  H01L21/7621 ,  H01L29/0638

摘要： A method for forming isolation regions in a semiconductor structure is provided. A mask comprising an upper and a lower layer of different materials is provided over the surface of the structure. A window is formed in the upper layer over the portions of the structure wherein the isolation regions are to be provided. Using the window in the upper layer as a mask, a larger window is formed in the lower layer by bringing a chemical etchant which etches only the lower layer into contact with the portions of the lower layer exposed by the window in the upper layer. The larger window formed in the lower layer is used as an etching mask to form an isolation groove, or depression, in the underlying semiconductor structure. The upper layer having the smaller window is used as an ion implantation mask for implanting particles into the bottom portion of the groove while masking the side portions of the grooves from the ions. With such method, lateral oxidation regions having self-registered anti-inversion regions which are located under the bottoms of the isolation regions and are spaced from the peripheries of the isolation regions by uniform, predetermined distances are obtained.

摘要翻译： 提供了一种在半导体结构中形成隔离区域的方法。 包含不同材料的上层和下层的掩模设置在结构的表面上。 在结构的部分上的上层中形成窗口，其中设置隔离区域。 使用上层的窗口作为掩模，通过使仅蚀刻下层的化学蚀刻剂与下层中的窗口暴露的下层的部分接触而在下层中形成较大的窗口。 在下层形成的较大的窗用作蚀刻掩模，以在下面的半导体结构中形成隔离槽或凹陷。 将具有较小窗口的上层用作离子注入掩模，用于将颗粒注入凹槽的底部，同时掩蔽凹槽的侧面与离子。 通过这样的方法，获得了位于隔离区底部以及隔离区域周围与均匀的预定距离隔开的具有自我登记的抗反转区域的横向氧化区域。

公开(公告)号：US4187125A

公开(公告)日：1980-02-05

申请号：US911659

申请日：1978-06-01

申请人： Wolfgang M. Feist

发明人： Wolfgang M. Feist

IPC分类号： H01L21/306 ,  H01L21/308 ,  H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L29/06 ,  H01L21/302

CPC分类号： H01L21/76 ,  H01L21/30608 ,  H01L21/308 ,  H01L21/7621 ,  H01L21/76216 ,  H01L21/764 ,  Y10S438/973

摘要： Semiconductor integrated circuit structures and manufacturing methods wherein isolation grooves are etched into a semiconductor body by first bringing an anisotropic etchant in contact with portions of the surface of the body which are exposed by windows formed in an etch-resistant mask to form grooves with side walls which intersect the surface at acute angles. Next, an isotropic etchant is brought in contact with the walls of the etched grooves to remove portions of the body which are underneath the etch-resistant mask such that the mask extends over the side walls of the resulting grooves, the bottom walls of such grooves are disposed under the windows and the side walls maintain acute angle intersection with the surface. Junction isolation regions are formed by ion implanting particles into the bottom walls of the grooves, the mask shielding the side walls from such particles. This self-aligning process accurately controls the placement of the junction isolation regions and thereby reduces the depth required for the grooves in providing dielectric isolation. Because the grooves have side walls which intersect the surface at acute angles, and because the grooves are relatively shallow because of the addition of accurately placed junction isolation regions, subsequent metallization processing is more readily controllable.

摘要翻译： 半导体集成电路结构和制造方法，其中通过首先使各向异性蚀刻剂与由形成在耐蚀刻掩模中的窗户露出的主体表面的部分接触形成半导体主体，以形成具有侧壁的凹槽 其以锐角与表面相交。 接下来，使各向同性蚀刻剂与蚀刻槽的壁接触以去除抗蚀剂掩模下方的主体部分，使得掩模在所得到的凹槽的侧壁上延伸，这些凹槽的底壁 设置在窗户下方，侧壁与表面保持锐角交叉。 通过将离子注入到槽的底壁中的方式形成结隔离区域，掩模将侧壁与这些颗粒屏蔽。 该自对准过程精确地控制结隔离区域的布置，从而减少沟槽提供电介质隔离所需的深度。 因为凹槽具有以锐角与表面相交的侧壁，并且由于添加精确放置的结隔离区，因为沟槽相对较浅，所以随后的金属化处理更易于控制。

公开(公告)号：US4054896A

公开(公告)日：1977-10-18

申请号：US283252

申请日：1972-08-23

申请人： Amos Picker ,  Wolfgang M. Feist

发明人： Amos Picker ,  Wolfgang M. Feist

IPC分类号： G09G1/18 ,  G09G1/22 ,  H01J29/39 ,  H01J31/58 ,  H01L27/14

CPC分类号： H01J29/39 ,  G09G1/18 ,  G09G1/22 ,  H01J31/585

摘要： A display system having a cathode ray tube signal generator in which a solid state junction target utilizes a layer of semiconductor material and a layer of dielectric material to form a junction. The signal generator may be of the monoscope type in which portions of the target are masked or it may be of the photosensitive type in which an image is projected onto the target. A signal derived from the signal generator is displayed on a second cathode ray tube.

摘要翻译： 具有阴极射线管信号发生器的显示系统，其中固态接合靶使用半导体材料层和电介质材料层以形成结。 信号发生器可以是单目镜型，其中目标的部分被掩蔽，或者它可以是将图像投影到目标上的感光类型。 从第二阴极射线管显示从信号发生器得到的信号。

公开(公告)号：US3956025A

公开(公告)日：1976-05-11

申请号：US454647

申请日：1974-03-25

申请人： Hermann Statz ,  Wolfgang M. Feist

发明人： Hermann Statz ,  Wolfgang M. Feist

IPC分类号： H01J29/45 ,  H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/06 ,  H01L29/78 ,  H01L31/00 ,  H01L31/0216 ,  H01L21/265

CPC分类号： H01L31/0216 ,  H01J29/451 ,  H01J29/455 ,  H01J9/233 ,  H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/0611 ,  H01L29/78 ,  H01L31/00 ,  Y10S257/917

摘要： A semiconductor structure having a surface insulating layer formed as a grid with charges implanted in the insulating material to prevent inversion and, hence, channeling between adjacent semiconductor regions, preferably for use in nonblooming vidicon. The method of manufacturing such a structure uses ion implantation to create immobile positive charges in a grid pattern in an insulating layer in regions spaced from the interface between the insulating layer and the semiconductor body. The insulating layer is of sufficient thickness that substantially all of the charge sites in the insulating layer are separated from the outer surface of the insulator by a sufficient distance to effectively prevent a negative electric field from reaching into the silicon.

摘要翻译： 具有表面绝缘层的半导体结构，其形成为格栅，电荷注入绝缘材料中，以防止反转，并因此在相邻的半导体区之间引导沟道，优选用于不起伏的虚像。 制造这种结构的方法使用离子注入来在与绝缘层和半导体本体之间的界面间隔开的区域中的绝缘层中以栅格图案形成固定的正电荷。 绝缘层具有足够的厚度，绝缘层中的基本上所有的电荷位置与绝缘体的外表面分开足够的距离，以有效地防止负电场进入硅。